sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1031

WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMMHUB_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32) + (vmid*2), 0);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1032

WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMMHUB_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32) + (vmid*2), 0);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1034

WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMMHUB_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32) + (vmid*2),

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1036

WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMMHUB_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32) + (vmid*2),

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1039

WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMMHUB_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32) + (vmid*2), lower_32_bits(base));

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1040

WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMMHUB_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32) + (vmid*2), upper_32_bits(base));

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1042

WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32) + (vmid*2), 0);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1043

WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32) + (vmid*2), 0);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1045

WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32) + (vmid*2),

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1047

WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32) + (vmid*2),

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1050

WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32) + (vmid*2), lower_32_bits(base));

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1051

WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32) + (vmid*2), upper_32_bits(base));

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

284

WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), sh_mem_config);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

285

WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), sh_mem_bases);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

312

WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) + vmid,

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

315

while (!(RREG32(SOC15_REG_OFFSET(

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

321

WREG32(SOC15_REG_OFFSET(ATHUB, 0,

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

326

WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid,

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

329

WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID16_PASID_MAPPING) + vmid,

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

332

while (!(RREG32(SOC15_REG_OFFSET(

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

338

WREG32(SOC15_REG_OFFSET(ATHUB, 0,

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

343

WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid,

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

363

WREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL),

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

377

SOC15_REG_OFFSET(SDMA0, 0,

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

379

SOC15_REG_OFFSET(SDMA1, 0,

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

425

value = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS));

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

428

WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS), value);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

433

hqd_base = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

436

reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++)

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

443

WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), data);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

472

WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO),

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

474

WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI),

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

476

WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR),

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

478

WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI),

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

480

WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1),

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

485

WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_RPTR),

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

490

WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE), data);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

517

for (reg = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

518

reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++)

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

544

SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_GFX_CONTEXT_CNTL) :

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

545

SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_CONTEXT_CNTL);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

643

act = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE));

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

648

if (low == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE)) &&

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

649

high == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE_HI)))

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

706

WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_DEQUEUE_REQUEST), type);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

710

temp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE));

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

769

reg = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

780

reg = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

813

WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG16_ADDR_RANGE_LO32),

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

815

WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG16_ADDR_RANGE_HI32),

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

818

WREG32(SOC15_REG_OFFSET(MMHUB, 0,

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

821

WREG32(SOC15_REG_OFFSET(MMHUB, 0,

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

825

WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG16_REQ), req);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

827

WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMMHUB_VM_INVALIDATE_ENG16_REQ),

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

830

while (!(RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG16_ACK)) &

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

834

while (!(RREG32(SOC15_REG_OFFSET(MMHUB, 0,

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

933

WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX), gfx_index_val);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

934

WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_CMD), sq_cmd);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

943

WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX), data);

sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

436

WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9), 0xCAFEDEAD);

sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

444

PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9), 0));

sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

448

tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9));

sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

482

ib->ptr[0] = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0);

sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

484

ib->ptr[2] = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0);

sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

486

ib->ptr[4] = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0);

sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

489

ib->ptr[i] = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0);

sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

790

WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9), 0xCAFEDEAD);

sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

800

PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9), 0, 0, 0));

sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

805

tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9));

sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

839

ib->ptr[0] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9), 0, 0, PACKETJ_TYPE0);

sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

888

tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1644

SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE),

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1660

SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE), 0);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2076

WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI),

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2078

WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO),

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2080

WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH),

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2152

tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2154

WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2157

WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR),

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2160

WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA),

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2164

WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2169

WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2197

WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2199

WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), list_size);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2202

WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2205

WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2211

WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_ADDR_0)

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2215

WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_DATA_0)

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2236

default_data = data = RREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2241

WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2247

WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2252

WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2264

data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2267

WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2275

WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY), data);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2277

data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2280

WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2), data);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2282

data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2285

WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3), data);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2287

data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2292

WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL), data);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2304

default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2309

WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2318

default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2323

WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2332

default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2337

WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2345

default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2350

WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2358

default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2363

WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2367

data = RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_RENDER_CONTROL));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2375

default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2380

WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2388

default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2393

WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2658

(SOC15_REG_OFFSET(GC, 0, mmVGT_INDEX_TYPE) - PACKET3_SET_UCONFIG_REG_START));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

352

adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3563

SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3568

SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3573

SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3578

SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4212

reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_GFX) + pipe_num;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4332

amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4554

mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4557

mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4560

mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4563

mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

357

SOC15_REG_OFFSET(GC, 0,

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

360

SOC15_REG_OFFSET(GC, 0,

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

363

SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_REQ);

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

365

SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ACK);

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

367

SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL);

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

369

SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_STATUS);

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

371

SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL);

sys/dev/drm/amd/amdgpu/gmc_v9_0.c

457

reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;

sys/dev/drm/amd/amdgpu/gmc_v9_0.c

459

reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

391

SOC15_REG_OFFSET(MMHUB, 0,

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

394

SOC15_REG_OFFSET(MMHUB, 0,

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

397

SOC15_REG_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_REQ);

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

399

SOC15_REG_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_ACK);

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

401

SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL);

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

403

SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_STATUS);

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

405

SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL);

sys/dev/drm/amd/amdgpu/mxgpu_ai.c

137

reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,

sys/dev/drm/amd/amdgpu/mxgpu_ai.c

141

WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0),

sys/dev/drm/amd/amdgpu/mxgpu_ai.c

143

WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1),

sys/dev/drm/amd/amdgpu/mxgpu_ai.c

145

WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2),

sys/dev/drm/amd/amdgpu/mxgpu_ai.c

147

WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3),

sys/dev/drm/amd/amdgpu/mxgpu_ai.c

179

RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,

sys/dev/drm/amd/amdgpu/mxgpu_ai.c

226

u32 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL));

sys/dev/drm/amd/amdgpu/mxgpu_ai.c

230

WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL), tmp);

sys/dev/drm/amd/amdgpu/mxgpu_ai.c

278

u32 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL));

sys/dev/drm/amd/amdgpu/mxgpu_ai.c

282

WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL), tmp);

sys/dev/drm/amd/amdgpu/mxgpu_ai.c

55

return RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,

sys/dev/drm/amd/amdgpu/mxgpu_ai.c

65

reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,

sys/dev/drm/amd/amdgpu/mxgpu_ai.h

56

#define AI_MAIBOX_CONTROL_TRN_OFFSET_BYTE SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_CONTROL) * 4

sys/dev/drm/amd/amdgpu/mxgpu_ai.h

57

#define AI_MAIBOX_CONTROL_RCV_OFFSET_BYTE SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_CONTROL) * 4 + 1

sys/dev/drm/amd/amdgpu/nbio_v6_1.c

213

return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_GPU_HDP_FLUSH_REQ);

sys/dev/drm/amd/amdgpu/nbio_v6_1.c

218

return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_GPU_HDP_FLUSH_DONE);

sys/dev/drm/amd/amdgpu/nbio_v6_1.c

223

return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2);

sys/dev/drm/amd/amdgpu/nbio_v6_1.c

228

return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2);

sys/dev/drm/amd/amdgpu/nbio_v6_1.c

64

amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(

sys/dev/drm/amd/amdgpu/nbio_v6_1.c

76

u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :

sys/dev/drm/amd/amdgpu/nbio_v6_1.c

77

SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE);

sys/dev/drm/amd/amdgpu/nbio_v7_0.c

224

return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ);

sys/dev/drm/amd/amdgpu/nbio_v7_0.c

229

return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_DONE);

sys/dev/drm/amd/amdgpu/nbio_v7_0.c

234

return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2);

sys/dev/drm/amd/amdgpu/nbio_v7_0.c

239

return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2);

sys/dev/drm/amd/amdgpu/nbio_v7_0.c

62

amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(

sys/dev/drm/amd/amdgpu/nbio_v7_0.c

74

u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :

sys/dev/drm/amd/amdgpu/nbio_v7_0.c

75

SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE);

sys/dev/drm/amd/amdgpu/nbio_v7_4.c

186

return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ);

sys/dev/drm/amd/amdgpu/nbio_v7_4.c

191

return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_DONE);

sys/dev/drm/amd/amdgpu/nbio_v7_4.c

196

return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2);

sys/dev/drm/amd/amdgpu/nbio_v7_4.c

201

return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2);

sys/dev/drm/amd/amdgpu/nbio_v7_4.c

60

amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(

sys/dev/drm/amd/amdgpu/nbio_v7_4.c

72

u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :

sys/dev/drm/amd/amdgpu/nbio_v7_4.c

73

SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE);

sys/dev/drm/amd/amdgpu/psp_v10_0.c

231

ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),

sys/dev/drm/amd/amdgpu/psp_v10_0.c

255

ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),

sys/dev/drm/amd/amdgpu/psp_v10_0.c

347

*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR);

sys/dev/drm/amd/amdgpu/psp_v10_0.c

348

*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA);

sys/dev/drm/amd/amdgpu/psp_v10_0.c

353

*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR);

sys/dev/drm/amd/amdgpu/psp_v10_0.c

354

*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA);

sys/dev/drm/amd/amdgpu/psp_v10_0.c

359

*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR);

sys/dev/drm/amd/amdgpu/psp_v10_0.c

360

*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA);

sys/dev/drm/amd/amdgpu/psp_v10_0.c

365

*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR);

sys/dev/drm/amd/amdgpu/psp_v10_0.c

366

*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA);

sys/dev/drm/amd/amdgpu/psp_v10_0.c

371

*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR);

sys/dev/drm/amd/amdgpu/psp_v10_0.c

372

*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA);

sys/dev/drm/amd/amdgpu/psp_v10_0.c

377

*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR);

sys/dev/drm/amd/amdgpu/psp_v10_0.c

378

*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA);

sys/dev/drm/amd/amdgpu/psp_v10_0.c

383

*sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR);

sys/dev/drm/amd/amdgpu/psp_v10_0.c

384

*sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA);

sys/dev/drm/amd/amdgpu/psp_v11_0.c

160

ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),

sys/dev/drm/amd/amdgpu/psp_v11_0.c

180

ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),

sys/dev/drm/amd/amdgpu/psp_v11_0.c

201

ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),

sys/dev/drm/amd/amdgpu/psp_v11_0.c

220

ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),

sys/dev/drm/amd/amdgpu/psp_v11_0.c

299

ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),

sys/dev/drm/amd/amdgpu/psp_v11_0.c

318

ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),

sys/dev/drm/amd/amdgpu/psp_v11_0.c

412

*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR);

sys/dev/drm/amd/amdgpu/psp_v11_0.c

413

*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA);

sys/dev/drm/amd/amdgpu/psp_v11_0.c

418

*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR);

sys/dev/drm/amd/amdgpu/psp_v11_0.c

419

*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA);

sys/dev/drm/amd/amdgpu/psp_v11_0.c

424

*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR);

sys/dev/drm/amd/amdgpu/psp_v11_0.c

425

*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA);

sys/dev/drm/amd/amdgpu/psp_v11_0.c

430

*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR);

sys/dev/drm/amd/amdgpu/psp_v11_0.c

431

*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA);

sys/dev/drm/amd/amdgpu/psp_v11_0.c

436

*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR);

sys/dev/drm/amd/amdgpu/psp_v11_0.c

437

*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA);

sys/dev/drm/amd/amdgpu/psp_v11_0.c

442

*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR);

sys/dev/drm/amd/amdgpu/psp_v11_0.c

443

*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA);

sys/dev/drm/amd/amdgpu/psp_v11_0.c

448

*sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR);

sys/dev/drm/amd/amdgpu/psp_v11_0.c

449

*sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA);

sys/dev/drm/amd/amdgpu/psp_v11_0.c

520

offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);

sys/dev/drm/amd/amdgpu/psp_v11_0.c

534

offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);

sys/dev/drm/amd/amdgpu/psp_v3_1.c

187

ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),

sys/dev/drm/amd/amdgpu/psp_v3_1.c

207

ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),

sys/dev/drm/amd/amdgpu/psp_v3_1.c

247

ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),

sys/dev/drm/amd/amdgpu/psp_v3_1.c

266

ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),

sys/dev/drm/amd/amdgpu/psp_v3_1.c

349

ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),

sys/dev/drm/amd/amdgpu/psp_v3_1.c

373

ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),

sys/dev/drm/amd/amdgpu/psp_v3_1.c

467

*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR);

sys/dev/drm/amd/amdgpu/psp_v3_1.c

468

*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA);

sys/dev/drm/amd/amdgpu/psp_v3_1.c

473

*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR);

sys/dev/drm/amd/amdgpu/psp_v3_1.c

474

*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA);

sys/dev/drm/amd/amdgpu/psp_v3_1.c

479

*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR);

sys/dev/drm/amd/amdgpu/psp_v3_1.c

480

*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA);

sys/dev/drm/amd/amdgpu/psp_v3_1.c

485

*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR);

sys/dev/drm/amd/amdgpu/psp_v3_1.c

486

*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA);

sys/dev/drm/amd/amdgpu/psp_v3_1.c

491

*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR);

sys/dev/drm/amd/amdgpu/psp_v3_1.c

492

*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA);

sys/dev/drm/amd/amdgpu/psp_v3_1.c

497

*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR);

sys/dev/drm/amd/amdgpu/psp_v3_1.c

498

*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA);

sys/dev/drm/amd/amdgpu/psp_v3_1.c

503

*sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR);

sys/dev/drm/amd/amdgpu/psp_v3_1.c

504

*sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA);

sys/dev/drm/amd/amdgpu/psp_v3_1.c

586

offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);

sys/dev/drm/amd/amdgpu/psp_v3_1.c

600

offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1529

def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1539

WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1542

def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL));

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1552

WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), data);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1556

def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1567

WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1570

def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL));

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1580

WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), data);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1594

def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1597

WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1601

def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL));

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1604

WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1608

def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1611

WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1615

def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL));

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1618

WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1673

data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1678

data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

825

def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

829

WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

832

def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

835

WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

844

def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

847

WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

850

def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

853

WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

856

def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

863

WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);

sys/dev/drm/amd/amdgpu/soc15.c

1032

data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));

sys/dev/drm/amd/amdgpu/soc15.c

1037

data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));

sys/dev/drm/amd/amdgpu/soc15.c

1042

data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));

sys/dev/drm/amd/amdgpu/soc15.c

1047

data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));

sys/dev/drm/amd/amdgpu/soc15.c

113

address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);

sys/dev/drm/amd/amdgpu/soc15.c

114

data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);

sys/dev/drm/amd/amdgpu/soc15.c

127

address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);

sys/dev/drm/amd/amdgpu/soc15.c

128

data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);

sys/dev/drm/amd/amdgpu/soc15.c

141

address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);

sys/dev/drm/amd/amdgpu/soc15.c

142

data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);

sys/dev/drm/amd/amdgpu/soc15.c

155

address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);

sys/dev/drm/amd/amdgpu/soc15.c

156

data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);

sys/dev/drm/amd/amdgpu/soc15.c

228

WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl);

sys/dev/drm/amd/amdgpu/soc15.c

260

WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0);

sys/dev/drm/amd/amdgpu/soc15.c

263

dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA));

sys/dev/drm/amd/amdgpu/soc15.c

323

if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))

sys/dev/drm/amd/amdgpu/soc15.c

325

else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2))

sys/dev/drm/amd/amdgpu/soc15.c

594

amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(

sys/dev/drm/amd/amdgpu/soc15.c

884

def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL));

sys/dev/drm/amd/amdgpu/soc15.c

898

WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data);

sys/dev/drm/amd/amdgpu/soc15.c

900

def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));

sys/dev/drm/amd/amdgpu/soc15.c

908

WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data);

sys/dev/drm/amd/amdgpu/soc15.c

916

def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));

sys/dev/drm/amd/amdgpu/soc15.c

938

WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data);

sys/dev/drm/amd/amdgpu/soc15.c

945

def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));

sys/dev/drm/amd/amdgpu/soc15.c

953

WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data);

sys/dev/drm/amd/amdgpu/soc15.c

961

def = data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));

sys/dev/drm/amd/amdgpu/soc15.c

971

WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0), data);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1021

WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_LMI_CTRL2), 0,

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1042

WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET),

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1046

WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET), 0,

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1057

WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN),

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1062

WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_STATUS), 0,

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1095

WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_RBC_RB_CNTL), 0,

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1133

WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2),

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1147

WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), 0,

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1168

PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1171

PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1174

PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1177

PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1181

PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1184

PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1187

PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1244

PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1309

PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_VMID), 0));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1313

PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1316

PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1319

PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_RBC_IB_SIZE), 0));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1347

PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1350

PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1353

PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1363

PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1366

PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1369

PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GP_SCRATCH8), 0));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1372

PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1399

amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_NO_OP), 0));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

556

tmp = PACKET0(SOC15_REG_OFFSET(UVD, j,

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

561

tmp = PACKET0(SOC15_REG_OFFSET(UVD, j,

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

566

tmp = PACKET0(SOC15_REG_OFFSET(UVD, j,

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

572

amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j,

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

576

amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j,

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

809

MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS),

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

813

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

815

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

819

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

821

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

826

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET0),

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

828

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE0), size);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

830

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

832

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

834

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET1), (1 << 21));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

835

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_UVD_HEAP_SIZE);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

837

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

839

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

841

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET2), (2 << 21));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

842

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE2),

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

845

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_GP_SCRATCH4), adev->uvd.max_handles);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

849

MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_CGC_CTRL),

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

853

MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN),

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

857

MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2),

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

862

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET),

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

873

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL),

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

882

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET),

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

886

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL),

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

890

MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN),

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

895

MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS),

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

902

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RBC_RB_CNTL), tmp);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

906

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_LO), ring->gpu_addr);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

907

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_HI), upper_32_bits(ring->gpu_addr));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

908

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_SIZE), ring->ring_size / 4);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

911

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET), 0);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

914

MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2),

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

917

MMSCH_V1_0_INSERT_DIRECT_POLL(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), 0x02, 0x02);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

947

WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_POWER_STATUS), 0,

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

962

WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_CGC_CTRL), 0,

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

966

WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN), 0,

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

970

WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_LMI_CTRL2),

sys/dev/drm/amd/amdgpu/vce_v4_0.c

1021

WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SYS_INT_EN), val,

sys/dev/drm/amd/amdgpu/vce_v4_0.c

114

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR),

sys/dev/drm/amd/amdgpu/vce_v4_0.c

117

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR2),

sys/dev/drm/amd/amdgpu/vce_v4_0.c

120

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR3),

sys/dev/drm/amd/amdgpu/vce_v4_0.c

131

RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

139

WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SOFT_RESET),

sys/dev/drm/amd/amdgpu/vce_v4_0.c

143

WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SOFT_RESET), 0,

sys/dev/drm/amd/amdgpu/vce_v4_0.c

163

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_LO), lower_32_bits(addr));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

164

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_HI), upper_32_bits(addr));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

167

data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_VMID));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

170

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_VMID), data);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

173

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_CTX_SIZE), size);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

176

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP), 0);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

184

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_HOST), 0x10000001);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

186

data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

190

data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

233

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_LO),

sys/dev/drm/amd/amdgpu/vce_v4_0.c

235

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_HI),

sys/dev/drm/amd/amdgpu/vce_v4_0.c

237

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_SIZE),

sys/dev/drm/amd/amdgpu/vce_v4_0.c

241

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_CTRL), 0x398000);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

242

MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_CACHE_CTRL), ~0x1, 0);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

243

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_SWAP_CNTL), 0);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

244

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_SWAP_CNTL1), 0);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

245

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VM_CTRL), 0);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

248

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,

sys/dev/drm/amd/amdgpu/vce_v4_0.c

251

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,

sys/dev/drm/amd/amdgpu/vce_v4_0.c

255

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,

sys/dev/drm/amd/amdgpu/vce_v4_0.c

258

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,

sys/dev/drm/amd/amdgpu/vce_v4_0.c

262

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,

sys/dev/drm/amd/amdgpu/vce_v4_0.c

265

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,

sys/dev/drm/amd/amdgpu/vce_v4_0.c

268

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,

sys/dev/drm/amd/amdgpu/vce_v4_0.c

271

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,

sys/dev/drm/amd/amdgpu/vce_v4_0.c

277

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET0),

sys/dev/drm/amd/amdgpu/vce_v4_0.c

279

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_SIZE0), size);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

283

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET1),

sys/dev/drm/amd/amdgpu/vce_v4_0.c

285

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_SIZE1), size);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

289

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET2),

sys/dev/drm/amd/amdgpu/vce_v4_0.c

291

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_SIZE2), size);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

293

MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_CTRL2), ~0x100, 0);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

294

MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_SYS_INT_EN),

sys/dev/drm/amd/amdgpu/vce_v4_0.c

299

MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS),

sys/dev/drm/amd/amdgpu/vce_v4_0.c

301

MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CNTL),

sys/dev/drm/amd/amdgpu/vce_v4_0.c

303

MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_SOFT_RESET),

sys/dev/drm/amd/amdgpu/vce_v4_0.c

306

MMSCH_V1_0_INSERT_DIRECT_POLL(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS),

sys/dev/drm/amd/amdgpu/vce_v4_0.c

311

MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS),

sys/dev/drm/amd/amdgpu/vce_v4_0.c

337

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR), lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

338

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR), lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

339

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_LO), ring->gpu_addr);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

340

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_HI), upper_32_bits(ring->gpu_addr));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

341

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_SIZE), ring->ring_size / 4);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

345

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR2), lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

346

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR2), lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

347

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_LO2), ring->gpu_addr);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

348

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_HI2), upper_32_bits(ring->gpu_addr));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

349

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_SIZE2), ring->ring_size / 4);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

353

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR3), lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

354

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR3), lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

355

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_LO3), ring->gpu_addr);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

356

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_HI3), upper_32_bits(ring->gpu_addr));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

357

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_SIZE3), ring->ring_size / 4);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

360

WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS), VCE_STATUS__JOB_BUSY_MASK,

sys/dev/drm/amd/amdgpu/vce_v4_0.c

363

WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CNTL), 1, ~0x200001);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

365

WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SOFT_RESET), 0,

sys/dev/drm/amd/amdgpu/vce_v4_0.c

372

WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS), 0, ~VCE_STATUS__JOB_BUSY_MASK);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

385

WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CNTL), 0, ~0x200001);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

388

WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SOFT_RESET),

sys/dev/drm/amd/amdgpu/vce_v4_0.c

393

WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS), 0, ~VCE_STATUS__JOB_BUSY_MASK);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

606

WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_A), 0, ~(1 << 16));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

607

WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING), 0x1FF000, ~0xFF9FF000);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

608

WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_REG_CLOCK_GATING), 0x3F, ~0x3F);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

609

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_B), 0x1FF);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

611

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_CTRL), 0x00398000);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

612

WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_CACHE_CTRL), 0x0, ~0x1);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

613

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_SWAP_CNTL), 0);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

614

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_SWAP_CNTL1), 0);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

615

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VM_CTRL), 0);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

622

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR0),

sys/dev/drm/amd/amdgpu/vce_v4_0.c

624

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_64BIT_BAR0),

sys/dev/drm/amd/amdgpu/vce_v4_0.c

626

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET0), 0);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

628

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR0),

sys/dev/drm/amd/amdgpu/vce_v4_0.c

630

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_64BIT_BAR0),

sys/dev/drm/amd/amdgpu/vce_v4_0.c

632

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET0), offset & ~0x0f000000);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

636

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_SIZE0), size);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

638

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR1), (adev->vce.gpu_addr >> 8));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

639

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_64BIT_BAR1), (adev->vce.gpu_addr >> 40) & 0xff);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

642

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET1), (offset & ~0x0f000000) | (1 << 24));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

643

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_SIZE1), size);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

645

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR2), (adev->vce.gpu_addr >> 8));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

646

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_64BIT_BAR2), (adev->vce.gpu_addr >> 40) & 0xff);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

649

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET2), (offset & ~0x0f000000) | (2 << 24));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

650

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_SIZE2), size);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

652

WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_CTRL2), 0x0, ~0x100);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

653

WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SYS_INT_EN),

sys/dev/drm/amd/amdgpu/vce_v4_0.c

66

return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

68

return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR2));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

70

return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR3));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

715

if (RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS) & AMDGPU_VCE_STATUS_BUSY_MASK) {

sys/dev/drm/amd/amdgpu/vce_v4_0.c

720

if (RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS) & AMDGPU_VCE_STATUS_BUSY_MASK) {

sys/dev/drm/amd/amdgpu/vce_v4_0.c

796

tmp = data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_ARB_CTRL));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

803

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_ARB_CTRL), data);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

820

data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_B));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

823

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_B), data);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

825

data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

828

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING), data);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

830

data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING_2));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

833

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING_2), data);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

835

data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_REG_CLOCK_GATING));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

837

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_REG_CLOCK_GATING), data);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

839

data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_DMA_DCLK_CTRL));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

844

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_DMA_DCLK_CTRL), data);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

846

data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_B));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

849

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_B), data);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

851

data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

853

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING), data);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

855

data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING_2));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

857

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING_2), data);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

859

data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_REG_CLOCK_GATING));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

861

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_REG_CLOCK_GATING), data);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

863

data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_DMA_DCLK_CTRL));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

868

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_DMA_DCLK_CTRL), data);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

88

return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

90

return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR2));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

910

uint32_t data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_A);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

913

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_A, data);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

916

data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

919

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING, data);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

92

return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR3));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1095

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0,

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1140

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1149

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0,

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1153

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1157

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1188

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0,

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1300

PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1303

PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1319

PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1339

PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1342

PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1345

PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1348

PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1352

PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1355

PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1358

PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1377

PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_VMID), 0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1381

PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1384

PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1387

PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_IB_SIZE), 0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1398

PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1401

PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1404

PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GP_SCRATCH8), 0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1407

PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1432

PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1435

PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1438

PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1623

PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1642

PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1665

PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_DATA0), 0, 0, PACKETJ_TYPE0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1669

PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_DATA1), 0, 0, PACKETJ_TYPE0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1673

PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1677

PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1681

PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_CMD), 0, 0, PACKETJ_TYPE0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1685

PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_CMD), 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE4));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1689

PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1693

PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1697

PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1701

PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1709

PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1736

PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_IB_VMID), 0, 0, PACKETJ_TYPE0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1740

PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JPEG_VMID), 0, 0, PACKETJ_TYPE0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1744

PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1748

PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1752

PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_IB_SIZE), 0, 0, PACKETJ_TYPE0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1756

PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1760

PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1768

PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1772

PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1776

PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_STATUS), 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE3));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1788

PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1792

PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1796

PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1832

PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1861

ring->ring[(*ptr)++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1880

reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1886

reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1898

reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_CNTL);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1904

reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1910

reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_CNTL);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1915

ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1917

ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1919

ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1937

reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_RPTR);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1943

reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_CNTL);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1993

amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

789

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0,

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

838

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

842

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

864

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

868

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

879

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN),

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

883

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SYS_INT_EN),

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

922

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0,

sys/dev/drm/amd/amdgpu/vega10_ih.c

215

tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL));

sys/dev/drm/amd/amdgpu/vega10_ih.c

217

WREG32_NO_KIQ(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL), tmp);

sys/dev/drm/amd/powerplay/smumgr/smu10_smumgr.c

53

reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);

sys/dev/drm/amd/powerplay/smumgr/smu9_smumgr.c

67

reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);

sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c

75

reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);