sys/dev/drm/amd/amdgpu/ci_dpm.c

4497

if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)

sys/dev/drm/amd/amdgpu/ci_dpm.c

4510

if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)

sys/dev/drm/amd/amdgpu/ci_dpm.c

4524

if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)

sys/dev/drm/amd/amdgpu/ci_dpm.c

4661

if (table->last > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)

sys/dev/drm/amd/amdgpu/ci_dpm.c

4697

if (table->last >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)

sys/dev/drm/amd/amdgpu/ci_dpm.c

4840

if (i >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)

sys/dev/drm/amd/amdgpu/ci_dpm.h

79

u32 mc_data[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];

sys/dev/drm/amd/amdgpu/ci_dpm.h

87

SMU7_Discrete_MCRegisterAddress mc_reg_address[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];

sys/dev/drm/amd/powerplay/inc/smu7_discrete.h

420

uint32_t value[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];

sys/dev/drm/amd/powerplay/inc/smu7_discrete.h

429

SMU7_Discrete_MCRegisterAddress address[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1730

PP_ASSERT_WITH_CODE(i < SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE,

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2554

PP_ASSERT_WITH_CODE((table->last <= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE),

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2586

PP_ASSERT_WITH_CODE((j < SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE),

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2602

PP_ASSERT_WITH_CODE((j < SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE),

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2618

PP_ASSERT_WITH_CODE((j < SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE),

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.h

50

uint32_t mc_data[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.h

58

SMU7_Discrete_MCRegisterAddress mc_reg_address[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];

sys/dev/drm/radeon/ci_dpm.c

4378

if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)

sys/dev/drm/radeon/ci_dpm.c

4390

if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)

sys/dev/drm/radeon/ci_dpm.c

4403

if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)

sys/dev/drm/radeon/ci_dpm.c

4414

if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)

sys/dev/drm/radeon/ci_dpm.c

4427

if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)

sys/dev/drm/radeon/ci_dpm.c

4546

if (table->last > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)

sys/dev/drm/radeon/ci_dpm.c

4582

if (table->last >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)

sys/dev/drm/radeon/ci_dpm.c

4725

if (i >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)

sys/dev/drm/radeon/ci_dpm.h

78

u32 mc_data[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];

sys/dev/drm/radeon/ci_dpm.h

86

SMU7_Discrete_MCRegisterAddress mc_reg_address[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];

sys/dev/drm/radeon/smu7_discrete.h

419

uint32_t value[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];

sys/dev/drm/radeon/smu7_discrete.h

428

SMU7_Discrete_MCRegisterAddress address[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];