sys/dev/drm/amd/powerplay/inc/smu73_discrete.h

367

typedef struct SMU73_Discrete_DpmTable SMU73_Discrete_DpmTable;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1015

offsetof(SMU73_Discrete_DpmTable, GraphicsLevel);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1231

offsetof(SMU73_Discrete_DpmTable, MemoryLevel);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1301

SMU73_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1423

SMU73_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1462

SMU73_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1559

struct SMU73_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1606

struct SMU73_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1824

struct SMU73_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1930

struct SMU73_Discrete_DpmTable *table = &(smu_data->smc_state_table);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2111

offsetof(SMU73_Discrete_DpmTable, SystemFlags),

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2113

sizeof(SMU73_Discrete_DpmTable) - 3 * sizeof(SMU73_PIDController),

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2283

offsetof(SMU73_Discrete_DpmTable,

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2328

return offsetof(SMU73_Discrete_DpmTable, UvdBootLevel);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2330

return offsetof(SMU73_Discrete_DpmTable, VceBootLevel);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2332

return offsetof(SMU73_Discrete_DpmTable, LowSclkInterruptThreshold);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2377

mm_boot_level_offset = smu_data->smu7_data.dpm_table_start + offsetof(SMU73_Discrete_DpmTable,

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2413

offsetof(SMU73_Discrete_DpmTable, VceBootLevel);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

243

offsetof(SMU73_Discrete_DpmTable, VRConfig);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

251

level_addr = table_start + offsetof(SMU73_Discrete_DpmTable, GraphicsLevel);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2557

offsetof(SMU73_Discrete_DpmTable, GraphicsLevel);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2560

offsetof(SMU73_Discrete_DpmTable, MemoryLevel);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

492

SMU73_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

757

struct SMU73_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

785

struct SMU73_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

823

struct SMU73_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

829

struct SMU73_Discrete_DpmTable *table)

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.h

42

struct SMU73_Discrete_DpmTable smc_state_table;