sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

189

CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable))

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1899

PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2358

PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 1);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

119

SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

187

SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

127

SMC_SYSCON_CLOCK_CNTL_0,

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

134

SMC_SYSCON_CLOCK_CNTL_0,

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

217

SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

277

SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);

sys/dev/drm/amd/powerplay/smumgr/smu7_smumgr.c

162

return ((0 == PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable))

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

114

SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

180

SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

120

SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

180

SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);

sys/dev/drm/radeon/ci_smc.c

139

u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);

sys/dev/drm/radeon/ci_smc.c

143

WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp);

sys/dev/drm/radeon/ci_smc.c

148

u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);

sys/dev/drm/radeon/ci_smc.c

152

WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp);

sys/dev/drm/radeon/ci_smc.c

157

u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);

sys/dev/drm/radeon/ci_smc.c

176

tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);

sys/dev/drm/radeon/si_smc.c

145

u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);

sys/dev/drm/radeon/si_smc.c

149

WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp);

sys/dev/drm/radeon/si_smc.c

154

u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);

sys/dev/drm/radeon/si_smc.c

158

WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp);

sys/dev/drm/radeon/si_smc.c

164

u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);

sys/dev/drm/radeon/si_smc.c

202

tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);