sys/dev/drm/i915/intel_cdclk.c

832

if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |

sys/dev/drm/i915/intel_cdclk.c

833

DPLL_CTRL1_SSC(SKL_DPLL0) |

sys/dev/drm/i915/intel_cdclk.c

834

DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=

sys/dev/drm/i915/intel_cdclk.c

835

DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))

sys/dev/drm/i915/intel_cdclk.c

838

switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {

sys/dev/drm/i915/intel_cdclk.c

839

case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):

sys/dev/drm/i915/intel_cdclk.c

840

case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):

sys/dev/drm/i915/intel_cdclk.c

841

case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):

sys/dev/drm/i915/intel_cdclk.c

842

case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):

sys/dev/drm/i915/intel_cdclk.c

845

case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):

sys/dev/drm/i915/intel_cdclk.c

846

case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):

sys/dev/drm/i915/intel_cdclk.c

850

MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));

sys/dev/drm/i915/intel_cdclk.c

950

val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |

sys/dev/drm/i915/intel_cdclk.c

951

DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));

sys/dev/drm/i915/intel_cdclk.c

952

val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);

sys/dev/drm/i915/intel_cdclk.c

955

SKL_DPLL0);

sys/dev/drm/i915/intel_cdclk.c

958

SKL_DPLL0);

sys/dev/drm/i915/intel_display.c

9386

if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL2))

sys/dev/drm/i915/intel_display.c

9464

if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))