Symbol: SE_SF
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
119
SE_SF(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_INDEX, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
120
SE_SF(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC0_UPDATE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
121
SE_SF(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC2_UPDATE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
122
SE_SF(AFMT_GENERIC_HDR, AFMT_GENERIC_HB0, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
123
SE_SF(AFMT_GENERIC_HDR, AFMT_GENERIC_HB1, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
124
SE_SF(AFMT_GENERIC_HDR, AFMT_GENERIC_HB2, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
125
SE_SF(AFMT_GENERIC_HDR, AFMT_GENERIC_HB3, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
126
SE_SF(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_CONT, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
127
SE_SF(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_SEND, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
128
SE_SF(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_LINE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
129
SE_SF(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_CONT, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
130
SE_SF(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_SEND, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
131
SE_SF(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_LINE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
132
SE_SF(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
133
SE_SF(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
134
SE_SF(DP_PIXEL_FORMAT, DP_DYN_RANGE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
135
SE_SF(DP_PIXEL_FORMAT, DP_YCBCR_RANGE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
136
SE_SF(HDMI_CONTROL, HDMI_PACKET_GEN_VERSION, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
137
SE_SF(HDMI_CONTROL, HDMI_KEEPOUT_MODE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
138
SE_SF(HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
139
SE_SF(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
140
SE_SF(HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
141
SE_SF(HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
142
SE_SF(HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
143
SE_SF(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
144
SE_SF(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
145
SE_SF(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
146
SE_SF(HDMI_GC, HDMI_GC_AVMUTE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
147
SE_SF(DP_MSE_RATE_CNTL, DP_MSE_RATE_X, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
148
SE_SF(DP_MSE_RATE_CNTL, DP_MSE_RATE_Y, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
149
SE_SF(DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
150
SE_SF(AFMT_AVI_INFO3, AFMT_AVI_INFO_VERSION, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
151
SE_SF(HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
152
SE_SF(HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
153
SE_SF(HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
154
SE_SF(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
155
SE_SF(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
156
SE_SF(DP_SEC_CNTL, DP_SEC_GSP1_ENABLE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
157
SE_SF(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
158
SE_SF(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
159
SE_SF(DP_SEC_CNTL, DP_SEC_AVI_ENABLE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
160
SE_SF(DP_SEC_CNTL, DP_SEC_MPG_ENABLE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
161
SE_SF(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
162
SE_SF(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
163
SE_SF(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
164
SE_SF(DP_STEER_FIFO, DP_STEER_FIFO_RESET, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
165
SE_SF(DP_VID_TIMING, DP_VID_M_N_GEN_EN, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
166
SE_SF(DP_VID_N, DP_VID_N, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
167
SE_SF(DP_VID_M, DP_VID_M, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
168
SE_SF(DIG_FE_CNTL, DIG_START, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
169
SE_SF(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
170
SE_SF(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
171
SE_SF(AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
172
SE_SF(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
173
SE_SF(HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
174
SE_SF(HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
175
SE_SF(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
176
SE_SF(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_LAYOUT_OVRD, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
177
SE_SF(AFMT_AUDIO_PACKET_CONTROL2, AFMT_60958_OSF_OVRD, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
178
SE_SF(HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
179
SE_SF(HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
180
SE_SF(HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUDIO_PRIORITY, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
181
SE_SF(HDMI_ACR_32_0, HDMI_ACR_CTS_32, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
182
SE_SF(HDMI_ACR_32_1, HDMI_ACR_N_32, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
183
SE_SF(HDMI_ACR_44_0, HDMI_ACR_CTS_44, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
184
SE_SF(HDMI_ACR_44_1, HDMI_ACR_N_44, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
185
SE_SF(HDMI_ACR_48_0, HDMI_ACR_CTS_48, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
186
SE_SF(HDMI_ACR_48_1, HDMI_ACR_N_48, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
187
SE_SF(AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
188
SE_SF(AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
189
SE_SF(AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
190
SE_SF(AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
191
SE_SF(AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
192
SE_SF(AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
193
SE_SF(AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
194
SE_SF(AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
195
SE_SF(AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
196
SE_SF(DP_SEC_AUD_N, DP_SEC_AUD_N, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
197
SE_SF(DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
198
SE_SF(DP_SEC_CNTL, DP_SEC_ASP_ENABLE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
199
SE_SF(DP_SEC_CNTL, DP_SEC_ATP_ENABLE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
200
SE_SF(DP_SEC_CNTL, DP_SEC_AIP_ENABLE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
201
SE_SF(DP_SEC_CNTL, DP_SEC_ACM_ENABLE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
202
SE_SF(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, mask_sh)
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
208
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_INDEX, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
209
SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB0, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
210
SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB1, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
211
SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB2, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
212
SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB3, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
213
SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_CONT, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
214
SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_SEND, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
215
SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_LINE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
216
SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_CONT, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
217
SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_SEND, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
218
SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_LINE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
219
SE_SF(DP0_DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
220
SE_SF(DP0_DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
221
SE_SF(DIG0_HDMI_CONTROL, HDMI_PACKET_GEN_VERSION, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
222
SE_SF(DIG0_HDMI_CONTROL, HDMI_KEEPOUT_MODE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
223
SE_SF(DIG0_HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
224
SE_SF(DIG0_HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
225
SE_SF(DIG0_HDMI_CONTROL, HDMI_DATA_SCRAMBLE_EN, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
226
SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
227
SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
228
SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
229
SE_SF(DIG0_HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
230
SE_SF(DIG0_AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
231
SE_SF(DIG0_HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
232
SE_SF(DIG0_HDMI_GC, HDMI_GC_AVMUTE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
233
SE_SF(DP0_DP_MSE_RATE_CNTL, DP_MSE_RATE_X, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
234
SE_SF(DP0_DP_MSE_RATE_CNTL, DP_MSE_RATE_Y, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
235
SE_SF(DP0_DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
236
SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
237
SE_SF(DP0_DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
238
SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP1_ENABLE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
239
SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
240
SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
241
SE_SF(DP0_DP_SEC_CNTL, DP_SEC_MPG_ENABLE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
242
SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
243
SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
244
SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
245
SE_SF(DP0_DP_STEER_FIFO, DP_STEER_FIFO_RESET, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
246
SE_SF(DP0_DP_VID_TIMING, DP_VID_M_N_GEN_EN, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
247
SE_SF(DP0_DP_VID_N, DP_VID_N, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
248
SE_SF(DP0_DP_VID_M, DP_VID_M, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
249
SE_SF(DIG0_DIG_FE_CNTL, DIG_START, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
250
SE_SF(DIG0_AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
251
SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
252
SE_SF(DIG0_HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
253
SE_SF(DIG0_HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
254
SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
255
SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_LAYOUT_OVRD, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
256
SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_60958_OSF_OVRD, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
257
SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
258
SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
259
SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUDIO_PRIORITY, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
260
SE_SF(DIG0_HDMI_ACR_32_0, HDMI_ACR_CTS_32, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
261
SE_SF(DIG0_HDMI_ACR_32_1, HDMI_ACR_N_32, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
262
SE_SF(DIG0_HDMI_ACR_44_0, HDMI_ACR_CTS_44, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
263
SE_SF(DIG0_HDMI_ACR_44_1, HDMI_ACR_N_44, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
264
SE_SF(DIG0_HDMI_ACR_48_0, HDMI_ACR_CTS_48, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
265
SE_SF(DIG0_HDMI_ACR_48_1, HDMI_ACR_N_48, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
266
SE_SF(DIG0_AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
267
SE_SF(DIG0_AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
268
SE_SF(DIG0_AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
269
SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
270
SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
271
SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
272
SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
273
SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
274
SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
275
SE_SF(DP0_DP_SEC_AUD_N, DP_SEC_AUD_N, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
276
SE_SF(DP0_DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
277
SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ASP_ENABLE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
278
SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ATP_ENABLE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
279
SE_SF(DP0_DP_SEC_CNTL, DP_SEC_AIP_ENABLE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
280
SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ACM_ENABLE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
281
SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
282
SE_SF(DIG0_AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
283
SE_SF(DIG0_HDMI_CONTROL, HDMI_CLOCK_CHANNEL_RATE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
284
SE_SF(DIG0_DIG_FE_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
285
SE_SF(DIG0_DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
286
SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
287
SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, mask_sh)
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
294
SE_SF(TMDS_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
295
SE_SF(TMDS_CNTL, TMDS_COLOR_FORMAT, mask_sh)
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
299
SE_SF(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
300
SE_SF(HDMI_CONTROL, HDMI_CLOCK_CHANNEL_RATE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
301
SE_SF(HDMI_CONTROL, HDMI_DATA_SCRAMBLE_EN, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
302
SE_SF(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
303
SE_SF(DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
304
SE_SF(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
305
SE_SF(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, mask_sh)
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
309
SE_SF(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
310
SE_SF(HDMI_CONTROL, HDMI_CLOCK_CHANNEL_RATE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
311
SE_SF(HDMI_CONTROL, HDMI_DATA_SCRAMBLE_EN, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
312
SE_SF(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
313
SE_SF(DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
314
SE_SF(DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, mask_sh)
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
318
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC0_UPDATE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
319
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC2_UPDATE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
320
SE_SF(DP0_DP_PIXEL_FORMAT, DP_DYN_RANGE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
321
SE_SF(DP0_DP_PIXEL_FORMAT, DP_YCBCR_RANGE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
322
SE_SF(DIG0_HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
323
SE_SF(DIG0_HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
324
SE_SF(DIG0_HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
325
SE_SF(DP0_DP_SEC_CNTL, DP_SEC_AVI_ENABLE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
326
SE_SF(DIG0_AFMT_AVI_INFO3, AFMT_AVI_INFO_VERSION, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
327
SE_SF(DP0_DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, mask_sh)
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
331
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
332
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
333
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
334
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC0_FRAME_UPDATE_PENDING, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
335
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC1_FRAME_UPDATE_PENDING, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
336
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC2_FRAME_UPDATE_PENDING, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
337
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC3_FRAME_UPDATE_PENDING, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
338
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_FRAME_UPDATE_PENDING, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
339
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC5_FRAME_UPDATE_PENDING, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
340
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC6_FRAME_UPDATE_PENDING, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
341
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC7_FRAME_UPDATE_PENDING, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
342
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC0_FRAME_UPDATE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
343
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC1_FRAME_UPDATE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
344
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC2_FRAME_UPDATE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
345
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC3_FRAME_UPDATE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
346
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_FRAME_UPDATE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
347
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC5_FRAME_UPDATE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
348
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC6_FRAME_UPDATE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
349
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC7_FRAME_UPDATE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
350
SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP4_ENABLE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
351
SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP5_ENABLE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
352
SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP6_ENABLE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
353
SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP7_ENABLE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
354
SE_SF(DP0_DP_DB_CNTL, DP_DB_DISABLE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
355
SE_SF(DP0_DP_MSA_COLORIMETRY, DP_MSA_MISC0, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
356
SE_SF(DP0_DP_MSA_TIMING_PARAM1, DP_MSA_HTOTAL, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
357
SE_SF(DP0_DP_MSA_TIMING_PARAM1, DP_MSA_VTOTAL, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
358
SE_SF(DP0_DP_MSA_TIMING_PARAM2, DP_MSA_HSTART, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
359
SE_SF(DP0_DP_MSA_TIMING_PARAM2, DP_MSA_VSTART, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
360
SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_HSYNCWIDTH, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
361
SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_HSYNCPOLARITY, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
362
SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_VSYNCWIDTH, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
363
SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_VSYNCPOLARITY, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
364
SE_SF(DP0_DP_MSA_TIMING_PARAM4, DP_MSA_HWIDTH, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
365
SE_SF(DP0_DP_MSA_TIMING_PARAM4, DP_MSA_VHEIGHT, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
366
SE_SF(DIG0_HDMI_DB_CONTROL, HDMI_DB_DISABLE, mask_sh),\
sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h
367
SE_SF(DP0_DP_VID_TIMING, DP_VID_N_MUL, mask_sh)
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
166
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_INDEX, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
167
SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB0, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
168
SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB1, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
169
SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB2, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
170
SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB3, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
171
SE_SF(DP0_DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
172
SE_SF(DP0_DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
173
SE_SF(DIG0_HDMI_CONTROL, HDMI_PACKET_GEN_VERSION, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
174
SE_SF(DIG0_HDMI_CONTROL, HDMI_KEEPOUT_MODE, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
175
SE_SF(DIG0_HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
176
SE_SF(DIG0_HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
177
SE_SF(DIG0_HDMI_CONTROL, HDMI_DATA_SCRAMBLE_EN, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
178
SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
179
SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
180
SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
181
SE_SF(DIG0_HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
182
SE_SF(DIG0_AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
183
SE_SF(DIG0_HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
184
SE_SF(DIG0_HDMI_GC, HDMI_GC_AVMUTE, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
185
SE_SF(DP0_DP_MSE_RATE_CNTL, DP_MSE_RATE_X, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
186
SE_SF(DP0_DP_MSE_RATE_CNTL, DP_MSE_RATE_Y, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
187
SE_SF(DP0_DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
188
SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
189
SE_SF(DP0_DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
190
SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP1_ENABLE, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
191
SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
192
SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
193
SE_SF(DP0_DP_SEC_CNTL, DP_SEC_MPG_ENABLE, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
194
SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
195
SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
196
SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
197
SE_SF(DP0_DP_STEER_FIFO, DP_STEER_FIFO_RESET, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
198
SE_SF(DP0_DP_VID_TIMING, DP_VID_M_N_GEN_EN, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
199
SE_SF(DP0_DP_VID_N, DP_VID_N, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
200
SE_SF(DP0_DP_VID_M, DP_VID_M, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
201
SE_SF(DIG0_DIG_FE_CNTL, DIG_START, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
202
SE_SF(DIG0_AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
203
SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
204
SE_SF(DIG0_HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
205
SE_SF(DIG0_HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
206
SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
207
SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_LAYOUT_OVRD, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
208
SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_60958_OSF_OVRD, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
209
SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
210
SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
211
SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUDIO_PRIORITY, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
212
SE_SF(DIG0_HDMI_ACR_32_0, HDMI_ACR_CTS_32, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
213
SE_SF(DIG0_HDMI_ACR_32_1, HDMI_ACR_N_32, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
214
SE_SF(DIG0_HDMI_ACR_44_0, HDMI_ACR_CTS_44, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
215
SE_SF(DIG0_HDMI_ACR_44_1, HDMI_ACR_N_44, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
216
SE_SF(DIG0_HDMI_ACR_48_0, HDMI_ACR_CTS_48, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
217
SE_SF(DIG0_HDMI_ACR_48_1, HDMI_ACR_N_48, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
218
SE_SF(DIG0_AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
219
SE_SF(DIG0_AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
220
SE_SF(DIG0_AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
221
SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
222
SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
223
SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
224
SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
225
SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
226
SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
227
SE_SF(DP0_DP_SEC_AUD_N, DP_SEC_AUD_N, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
228
SE_SF(DP0_DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
229
SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ASP_ENABLE, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
230
SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ATP_ENABLE, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
231
SE_SF(DP0_DP_SEC_CNTL, DP_SEC_AIP_ENABLE, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
232
SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ACM_ENABLE, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
233
SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
234
SE_SF(DIG0_AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
235
SE_SF(DIG0_HDMI_CONTROL, HDMI_CLOCK_CHANNEL_RATE, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
236
SE_SF(DIG0_DIG_FE_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
237
SE_SF(DIG0_DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
238
SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
239
SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
240
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
241
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
242
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
243
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC0_FRAME_UPDATE_PENDING, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
244
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC1_FRAME_UPDATE_PENDING, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
245
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC2_FRAME_UPDATE_PENDING, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
246
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC3_FRAME_UPDATE_PENDING, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
247
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_FRAME_UPDATE_PENDING, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
248
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC5_FRAME_UPDATE_PENDING, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
249
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC6_FRAME_UPDATE_PENDING, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
250
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC7_FRAME_UPDATE_PENDING, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
251
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC0_FRAME_UPDATE, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
252
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC1_FRAME_UPDATE, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
253
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC2_FRAME_UPDATE, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
254
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC3_FRAME_UPDATE, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
255
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_FRAME_UPDATE, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
256
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC5_FRAME_UPDATE, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
257
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC6_FRAME_UPDATE, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
258
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC7_FRAME_UPDATE, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
259
SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP4_ENABLE, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
260
SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP5_ENABLE, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
261
SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP6_ENABLE, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
262
SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP7_ENABLE, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
263
SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP7_SEND, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
264
SE_SF(DP0_DP_DB_CNTL, DP_DB_DISABLE, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
265
SE_SF(DP0_DP_MSA_COLORIMETRY, DP_MSA_MISC0, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
266
SE_SF(DP0_DP_MSA_TIMING_PARAM1, DP_MSA_HTOTAL, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
267
SE_SF(DP0_DP_MSA_TIMING_PARAM1, DP_MSA_VTOTAL, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
268
SE_SF(DP0_DP_MSA_TIMING_PARAM2, DP_MSA_HSTART, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
269
SE_SF(DP0_DP_MSA_TIMING_PARAM2, DP_MSA_VSTART, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
270
SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_HSYNCWIDTH, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
271
SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_HSYNCPOLARITY, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
272
SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_VSYNCWIDTH, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
273
SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_VSYNCPOLARITY, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
274
SE_SF(DP0_DP_MSA_TIMING_PARAM4, DP_MSA_HWIDTH, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
275
SE_SF(DP0_DP_MSA_TIMING_PARAM4, DP_MSA_VHEIGHT, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
276
SE_SF(DIG0_HDMI_DB_CONTROL, HDMI_DB_DISABLE, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
277
SE_SF(DP0_DP_VID_TIMING, DP_VID_N_MUL, mask_sh)
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
284
SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_CONT, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
285
SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_SEND, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
286
SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_LINE, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
287
SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_CONT, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
288
SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_SEND, mask_sh),\
sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
289
SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_LINE, mask_sh)