sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

295

retval = m->sdma_engine_id * SDMA1_REGISTER_OFFSET +

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

491

uint32_t sdma_offset = engine_id * SDMA1_REGISTER_OFFSET +

sys/dev/drm/amd/amdgpu/cik_sdma.c

1100

tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);

sys/dev/drm/amd/amdgpu/cik_sdma.c

1102

WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);

sys/dev/drm/amd/amdgpu/cik_sdma.c

1153

sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);

sys/dev/drm/amd/amdgpu/cik_sdma.c

1155

WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);

sys/dev/drm/amd/amdgpu/cik_sdma.c

1158

sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);

sys/dev/drm/amd/amdgpu/cik_sdma.c

1160

WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);

sys/dev/drm/amd/amdgpu/cik_sdma.c

48

SDMA1_REGISTER_OFFSET

sys/dev/drm/amd/amdgpu/cik_sdma.c

904

WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100);

sys/dev/drm/amd/amdgpu/cik_sdma.c

911

orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET);

sys/dev/drm/amd/amdgpu/cik_sdma.c

914

WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data);

sys/dev/drm/amd/amdgpu/cik_sdma.c

929

orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);

sys/dev/drm/amd/amdgpu/cik_sdma.c

932

WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);

sys/dev/drm/amd/amdgpu/cik_sdma.c

939

orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);

sys/dev/drm/amd/amdgpu/cik_sdma.c

942

WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

1045

sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

1047

WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

1050

sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

1052

WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

60

SDMA1_REGISTER_OFFSET

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

992

tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

994

WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

1380

sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

1382

WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

1385

sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

1387

WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

74

SDMA1_REGISTER_OFFSET

sys/dev/drm/amd/amdgpu/vi.c

482

{mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET},

sys/dev/drm/radeon/cik.c

157

case (SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET):

sys/dev/drm/radeon/cik.c

3354

WREG32(SDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET, gb_addr_config & 0x70);

sys/dev/drm/radeon/cik.c

4840

RREG32(SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET));

sys/dev/drm/radeon/cik.c

4897

tmp = RREG32(SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET);

sys/dev/drm/radeon/cik.c

4986

tmp = RREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET);

sys/dev/drm/radeon/cik.c

4988

WREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET, tmp);

sys/dev/drm/radeon/cik.c

5187

tmp = RREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET);

sys/dev/drm/radeon/cik.c

5189

WREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET, tmp);

sys/dev/drm/radeon/cik.c

5540

WREG32(SDMA0_GFX_VIRTUAL_ADDR + SDMA1_REGISTER_OFFSET, 0);

sys/dev/drm/radeon/cik.c

5541

WREG32(SDMA0_GFX_APE1_CNTL + SDMA1_REGISTER_OFFSET, 0);

sys/dev/drm/radeon/cik.c

6187

WREG32(SDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100);

sys/dev/drm/radeon/cik.c

6194

orig = data = RREG32(SDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET);

sys/dev/drm/radeon/cik.c

6197

WREG32(SDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data);

sys/dev/drm/radeon/cik.c

6212

orig = data = RREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);

sys/dev/drm/radeon/cik.c

6215

WREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);

sys/dev/drm/radeon/cik.c

6222

orig = data = RREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);

sys/dev/drm/radeon/cik.c

6225

WREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);

sys/dev/drm/radeon/cik.c

6892

tmp = RREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;

sys/dev/drm/radeon/cik.c

6893

WREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET, tmp);

sys/dev/drm/radeon/cik.c

7076

dma_cntl1 = RREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;

sys/dev/drm/radeon/cik.c

7247

WREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET, dma_cntl1);

sys/dev/drm/radeon/cik_sdma.c

117

reg = SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET;

sys/dev/drm/radeon/cik_sdma.c

261

reg_offset = SDMA1_REGISTER_OFFSET;

sys/dev/drm/radeon/cik_sdma.c

311

reg_offset = SDMA1_REGISTER_OFFSET;

sys/dev/drm/radeon/cik_sdma.c

343

reg_offset = SDMA1_REGISTER_OFFSET;

sys/dev/drm/radeon/cik_sdma.c

378

reg_offset = SDMA1_REGISTER_OFFSET;

sys/dev/drm/radeon/cik_sdma.c

491

WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0);

sys/dev/drm/radeon/cik_sdma.c

493

WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, le32_to_cpup(fw_data++));

sys/dev/drm/radeon/cik_sdma.c

494

WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION);

sys/dev/drm/radeon/cik_sdma.c

507

WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0);

sys/dev/drm/radeon/cik_sdma.c

509

WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, be32_to_cpup(fw_data++));

sys/dev/drm/radeon/cik_sdma.c

510

WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION);

sys/dev/drm/radeon/cik_sdma.c

514

WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0);

sys/dev/drm/radeon/cik_sdma.c

72

reg = SDMA0_GFX_RB_RPTR + SDMA1_REGISTER_OFFSET;

sys/dev/drm/radeon/cik_sdma.c

96

reg = SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET;