sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

379

SOC15_REG_OFFSET(SDMA1, 0,

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

544

SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_GFX_CONTEXT_CNTL) :

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

279

ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

453

ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

101

SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

102

SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104001),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

103

SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001)

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1542

def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL));

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1552

WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), data);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

156

SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

157

SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1570

def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL));

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

158

SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1580

WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), data);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

159

SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

160

SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1601

def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL));

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1604

WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

161

SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1615

def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL));

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1618

WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

162

SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

163

SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

164

SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RD_BURST_CNTL, 0x0000000f, 0x00000003),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

165

SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

166

SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

167

SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

168

SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

169

SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

170

SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

171

SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

172

SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

173

SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

174

SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

175

SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

176

SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

177

SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

178

SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

179

SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

180

SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

181

SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

182

SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_WATERMK, 0xFE000000, 0x00000000),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

76

SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

77

SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_IB_CNTL, 0x800f0100, 0x00000100),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

78

SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

79

SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_IB_CNTL, 0x800f0100, 0x00000100),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

80

SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

81

SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_POWER_CNTL, 0x003ff000, 0x0003c000),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

82

SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_IB_CNTL, 0x800f0100, 0x00000100),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

83

SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

84

SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_IB_CNTL, 0x800f0100, 0x00000100),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

85

SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

86

SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

87

SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_WATERMK, 0xfc000000, 0x00000000)

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

93

SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

94

SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

95

SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002)

sys/dev/drm/amd/amdgpu/soc15.c

285

{ SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},

sys/dev/drm/radeon/cik_sdma.c

178

ref_and_mask = SDMA1;