sys/dev/drm/amd/amdgpu/cik_sdma.c

1093

tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);

sys/dev/drm/amd/amdgpu/cik_sdma.c

1095

WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);

sys/dev/drm/amd/amdgpu/cik_sdma.c

1137

sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);

sys/dev/drm/amd/amdgpu/cik_sdma.c

1139

WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);

sys/dev/drm/amd/amdgpu/cik_sdma.c

1142

sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);

sys/dev/drm/amd/amdgpu/cik_sdma.c

1144

WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);

sys/dev/drm/amd/amdgpu/cik_sdma.c

47

SDMA0_REGISTER_OFFSET,

sys/dev/drm/amd/amdgpu/cik_sdma.c

903

WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100);

sys/dev/drm/amd/amdgpu/cik_sdma.c

906

orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET);

sys/dev/drm/amd/amdgpu/cik_sdma.c

909

WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data);

sys/dev/drm/amd/amdgpu/cik_sdma.c

924

orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);

sys/dev/drm/amd/amdgpu/cik_sdma.c

927

WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);

sys/dev/drm/amd/amdgpu/cik_sdma.c

934

orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);

sys/dev/drm/amd/amdgpu/cik_sdma.c

937

WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

1029

sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

1031

WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

1034

sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

1036

WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

59

SDMA0_REGISTER_OFFSET,

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

985

tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

987

WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

1364

sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

1366

WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

1369

sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

1371

WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

73

SDMA0_REGISTER_OFFSET,

sys/dev/drm/amd/amdgpu/vi.c

481

{mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET},

sys/dev/drm/radeon/cik.c

156

case (SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET):

sys/dev/drm/radeon/cik.c

3353

WREG32(SDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET, gb_addr_config & 0x70);

sys/dev/drm/radeon/cik.c

4838

RREG32(SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET));

sys/dev/drm/radeon/cik.c

4892

tmp = RREG32(SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET);

sys/dev/drm/radeon/cik.c

4980

tmp = RREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET);

sys/dev/drm/radeon/cik.c

4982

WREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET, tmp);

sys/dev/drm/radeon/cik.c

5183

tmp = RREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET);

sys/dev/drm/radeon/cik.c

5185

WREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET, tmp);

sys/dev/drm/radeon/cik.c

5538

WREG32(SDMA0_GFX_VIRTUAL_ADDR + SDMA0_REGISTER_OFFSET, 0);

sys/dev/drm/radeon/cik.c

5539

WREG32(SDMA0_GFX_APE1_CNTL + SDMA0_REGISTER_OFFSET, 0);

sys/dev/drm/radeon/cik.c

6186

WREG32(SDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100);

sys/dev/drm/radeon/cik.c

6189

orig = data = RREG32(SDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET);

sys/dev/drm/radeon/cik.c

6192

WREG32(SDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data);

sys/dev/drm/radeon/cik.c

6207

orig = data = RREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);

sys/dev/drm/radeon/cik.c

6210

WREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);

sys/dev/drm/radeon/cik.c

6217

orig = data = RREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);

sys/dev/drm/radeon/cik.c

6220

WREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);

sys/dev/drm/radeon/cik.c

6890

tmp = RREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;

sys/dev/drm/radeon/cik.c

6891

WREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET, tmp);

sys/dev/drm/radeon/cik.c

7075

dma_cntl = RREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;

sys/dev/drm/radeon/cik.c

7246

WREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET, dma_cntl);

sys/dev/drm/radeon/cik_sdma.c

115

reg = SDMA0_GFX_RB_WPTR + SDMA0_REGISTER_OFFSET;

sys/dev/drm/radeon/cik_sdma.c

259

reg_offset = SDMA0_REGISTER_OFFSET;

sys/dev/drm/radeon/cik_sdma.c

309

reg_offset = SDMA0_REGISTER_OFFSET;

sys/dev/drm/radeon/cik_sdma.c

341

reg_offset = SDMA0_REGISTER_OFFSET;

sys/dev/drm/radeon/cik_sdma.c

374

reg_offset = SDMA0_REGISTER_OFFSET;

sys/dev/drm/radeon/cik_sdma.c

482

WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0);

sys/dev/drm/radeon/cik_sdma.c

484

WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, le32_to_cpup(fw_data++));

sys/dev/drm/radeon/cik_sdma.c

485

WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION);

sys/dev/drm/radeon/cik_sdma.c

500

WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0);

sys/dev/drm/radeon/cik_sdma.c

502

WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, be32_to_cpup(fw_data++));

sys/dev/drm/radeon/cik_sdma.c

503

WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION);

sys/dev/drm/radeon/cik_sdma.c

513

WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0);

sys/dev/drm/radeon/cik_sdma.c

70

reg = SDMA0_GFX_RB_RPTR + SDMA0_REGISTER_OFFSET;

sys/dev/drm/radeon/cik_sdma.c

94

reg = SDMA0_GFX_RB_WPTR + SDMA0_REGISTER_OFFSET;