sys/dev/drm/amd/amdgpu/sdma_v2_4.c

346

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

434

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

436

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

437

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

454

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

463

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

520

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

672

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

674

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

675

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

693

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

731

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

573

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

704

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

706

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

707

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

724

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

786

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);

sys/dev/drm/radeon/cik_sdma.c

262

rb_cntl = RREG32(SDMA0_GFX_RB_CNTL + reg_offset);

sys/dev/drm/radeon/cik_sdma.c

264

WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl);

sys/dev/drm/radeon/cik_sdma.c

391

WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl);

sys/dev/drm/radeon/cik_sdma.c

413

WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl | SDMA_RB_ENABLE);