sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

377

SOC15_REG_OFFSET(SDMA0, 0,

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

545

SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_CONTEXT_CNTL);

sys/dev/drm/amd/amdgpu/psp_v10_0.c

383

*sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR);

sys/dev/drm/amd/amdgpu/psp_v10_0.c

384

*sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA);

sys/dev/drm/amd/amdgpu/psp_v11_0.c

448

*sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR);

sys/dev/drm/amd/amdgpu/psp_v11_0.c

449

*sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA);

sys/dev/drm/amd/amdgpu/psp_v3_1.c

503

*sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR);

sys/dev/drm/amd/amdgpu/psp_v3_1.c

504

*sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

277

ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

451

ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

100

SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

107

SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

108

SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

109

SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

110

SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

111

SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0xfc3fffff, 0x40000051),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

112

SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

113

SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

114

SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

115

SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

116

SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

117

SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000)

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

121

SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

126

SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

127

SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

128

SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

129

SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

130

SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

131

SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

132

SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

133

SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

134

SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RD_BURST_CNTL, 0x0000000f, 0x00000003),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

135

SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

136

SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

137

SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

138

SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

139

SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

140

SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

141

SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

142

SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

143

SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

144

SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

145

SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

146

SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

147

SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

148

SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

149

SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

150

SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

151

SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

152

SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xFE000000, 0x00000000),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1529

def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1539

WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1556

def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1567

WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1594

def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1597

WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1608

def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1611

WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1673

data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1678

data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

187

SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

188

SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002)

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

193

SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00003001),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

194

SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00003001)

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

63

SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

64

SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xff000ff0, 0x3f000100),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

65

SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0100, 0x00000100),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

66

SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

67

SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_IB_CNTL, 0x800f0100, 0x00000100),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

68

SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

69

SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003ff006, 0x0003c000),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

70

SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0100, 0x00000100),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

71

SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

72

SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0100, 0x00000100),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

73

SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

74

SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

75

SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

825

def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

829

WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

832

def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

835

WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

844

def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

847

WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

850

def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

853

WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

856

def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

863

WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

91

SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

92

SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

99

SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104001),

sys/dev/drm/amd/amdgpu/soc15.c

284

{ SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},

sys/dev/drm/radeon/cik_sdma.c

176

ref_and_mask = SDMA0;