sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

229

reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) &

sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

265

RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF);

sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

284

reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) &

sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

297

reg_data2 = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS);

sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

325

RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF);

sys/dev/drm/amd/amdgpu/df_v1_7.c

100

tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);

sys/dev/drm/amd/amdgpu/df_v1_7.c

42

tmp = RREG32_SOC15(DF, 0, mmFabricConfigAccessControl);

sys/dev/drm/amd/amdgpu/df_v1_7.c

54

tmp = RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0);

sys/dev/drm/amd/amdgpu/df_v1_7.c

79

tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);

sys/dev/drm/amd/amdgpu/df_v1_7.c

84

tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);

sys/dev/drm/amd/amdgpu/df_v3_6.c

103

tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);

sys/dev/drm/amd/amdgpu/df_v3_6.c

43

tmp = RREG32_SOC15(DF, 0, mmFabricConfigAccessControl);

sys/dev/drm/amd/amdgpu/df_v3_6.c

55

tmp = RREG32_SOC15(DF, 0, mmDF_CS_UMC_AON0_DramBaseAddress0);

sys/dev/drm/amd/amdgpu/df_v3_6.c

82

tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);

sys/dev/drm/amd/amdgpu/df_v3_6.c

87

tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1042

data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1315

return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1330

*(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1418

gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1538

adev->gfx.ngg.gds_reserve_addr = RREG32_SOC15(GC, 0, mmGDS_VMID0_BASE);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1539

adev->gfx.ngg.gds_reserve_addr += RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1893

data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1894

data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1972

adev->gfx.config.db_debug2 = RREG32_SOC15(GC, 0, mmDB_DEBUG2);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2032

if (RREG32_SOC15(GC, 0, mmRLC_SERDES_CU_MASTER_BUSY) == 0)

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2054

if ((RREG32_SOC15(GC, 0, mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2063

u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2454

rlc_ucode_ver = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_6);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2535

u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2711

tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2802

tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2907

tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2914

tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2944

tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2954

tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2982

tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2998

mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3003

tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3008

tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3041

if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3044

if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3129

if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3134

if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3459

if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3486

tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3505

tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3522

tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3526

tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3532

tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3547

clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) |

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3548

((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3621

rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3634

if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3650

rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3710

def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3729

def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3736

def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3744

def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3758

data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3765

data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3783

def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3791

def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3802

def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3809

def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3829

def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3841

def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3852

def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3858

def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3979

data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3984

data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3993

data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3998

data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4003

data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4026

wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4027

wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4966

data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4967

data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

993

data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7);

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

114

tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL);

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

135

tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL);

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

146

tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL2);

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

173

tmp = RREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL);

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

295

tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL);

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

318

tmp = RREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL);

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

35

return (u64)RREG32_SOC15(GC, 0, mmMC_VM_FB_OFFSET) << 24;

sys/dev/drm/amd/amdgpu/gfxhub_v1_1.c

33

u32 xgmi_lfb_cntl = RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_CNTL);

sys/dev/drm/amd/amdgpu/gfxhub_v1_1.c

48

RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_SIZE),

sys/dev/drm/amd/amdgpu/gmc_v9_0.c

1123

tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL);

sys/dev/drm/amd/amdgpu/gmc_v9_0.c

882

u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);

sys/dev/drm/amd/amdgpu/gmc_v9_0.c

900

viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);

sys/dev/drm/amd/amdgpu/gmc_v9_0.c

911

viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE);

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

123

tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2);

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

134

tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL);

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

155

tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL);

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

166

tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2);

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

191

tmp = RREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_CNTL);

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

327

tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL);

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

336

tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL);

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

351

tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL);

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

40

u64 base = RREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE);

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

41

u64 top = RREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_TOP);

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

414

def = data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG);

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

417

def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

418

def2 = data2 = RREG32_SOC15(MMHUB, 0, mmDAGB1_CNTL_MISC2);

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

420

def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_RV);

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

477

def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

493

def = data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG);

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

509

def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

556

data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

561

data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG);

sys/dev/drm/amd/amdgpu/nbio_v6_1.c

120

u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE);

sys/dev/drm/amd/amdgpu/nbio_v6_1.c

137

interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL);

sys/dev/drm/amd/amdgpu/nbio_v6_1.c

250

reg = RREG32_SOC15(NBIO, 0, mmRCC_PF_0_0_RCC_IOV_FUNC_IDENTIFIER);

sys/dev/drm/amd/amdgpu/nbio_v6_1.c

38

u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);

sys/dev/drm/amd/amdgpu/nbio_v6_1.c

70

return RREG32_SOC15(NBIO, 0, mmRCC_PF_0_0_RCC_CONFIG_MEMSIZE);

sys/dev/drm/amd/amdgpu/nbio_v7_0.c

103

u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE);

sys/dev/drm/amd/amdgpu/nbio_v7_0.c

119

data = RREG32_SOC15(NBIO, 0, mmSYSHUB_DATA);

sys/dev/drm/amd/amdgpu/nbio_v7_0.c

212

interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL);

sys/dev/drm/amd/amdgpu/nbio_v7_0.c

39

u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);

sys/dev/drm/amd/amdgpu/nbio_v7_0.c

68

return RREG32_SOC15(NBIO, 0, mmRCC_CONFIG_MEMSIZE);

sys/dev/drm/amd/amdgpu/nbio_v7_4.c

114

u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE);

sys/dev/drm/amd/amdgpu/nbio_v7_4.c

174

interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL);

sys/dev/drm/amd/amdgpu/nbio_v7_4.c

223

reg = RREG32_SOC15(NBIO, 0, mmRCC_IOV_FUNC_IDENTIFIER);

sys/dev/drm/amd/amdgpu/nbio_v7_4.c

37

u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);

sys/dev/drm/amd/amdgpu/nbio_v7_4.c

66

return RREG32_SOC15(NBIO, 0, mmRCC_CONFIG_MEMSIZE);

sys/dev/drm/amd/amdgpu/psp_v10_0.c

295

psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);

sys/dev/drm/amd/amdgpu/psp_v11_0.c

155

sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);

sys/dev/drm/amd/amdgpu/psp_v11_0.c

196

sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);

sys/dev/drm/amd/amdgpu/psp_v11_0.c

221

RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81),

sys/dev/drm/amd/amdgpu/psp_v11_0.c

358

psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);

sys/dev/drm/amd/amdgpu/psp_v3_1.c

182

sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);

sys/dev/drm/amd/amdgpu/psp_v3_1.c

242

sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);

sys/dev/drm/amd/amdgpu/psp_v3_1.c

267

RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81),

sys/dev/drm/amd/amdgpu/psp_v3_1.c

270

ver = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58);

sys/dev/drm/amd/amdgpu/psp_v3_1.c

413

psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);

sys/dev/drm/amd/amdgpu/psp_v3_1.c

576

reg = RREG32_SOC15(NBIO, 0, mmPCIE_DATA2);

sys/dev/drm/amd/amdgpu/soc15.c

171

r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA);

sys/dev/drm/amd/amdgpu/soc15.c

193

r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA);

sys/dev/drm/amd/amdgpu/soc15_common.h

80

RREG32_SOC15(ip, inst, mmUVD_DPG_LMA_DATA); })

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1032

status = RREG32_SOC15(UVD, k, mmUVD_STATUS);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

106

return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1091

ring->wptr = RREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

124

return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1248

tmp = RREG32_SOC15(UVD, ring->me, mmUVD_CONTEXT_ID);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

126

return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1468

(RREG32_SOC15(UVD, ring->me, mmUVD_STATUS) &

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1591

data = RREG32_SOC15(UVD, ring->me, mmUVD_CGC_CTRL);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1592

data1 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1593

data2 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_CTRL);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1647

data = RREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1648

data1 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

382

harvest = RREG32_SOC15(UVD, i, mmUVD_PG0_CC_UVD_HARVESTING);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

733

data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_VMID);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

75

return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_RPTR);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

755

data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

759

data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

90

return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

92

return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR2);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1091

ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1100

ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1178

int tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1210

return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1253

return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1267

return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1454

return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1456

return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1471

return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1473

return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1580

return RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1594

return RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

225

if (RREG32_SOC15(VCN, 0, mmUVD_STATUS))

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

434

data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

445

data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

450

data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

460

data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

483

data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

507

data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

534

data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

561

data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

570

data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

575

data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

584

data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

607

data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

713

data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

728

data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

782

tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

793

tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

806

tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

832

RREG32_SOC15(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK) | 0x3);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

845

tmp = RREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

854

status = RREG32_SOC15(UVD, 0, mmUVD_STATUS);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

888

tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) & ~UVD_STATUS__UVD_BUSY;

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

918

ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

950

ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

971

tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS);

sys/dev/drm/amd/amdgpu/vega10_ih.c

100

ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL);

sys/dev/drm/amd/amdgpu/vega10_ih.c

138

ih_doorbell_rtpr = RREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR);

sys/dev/drm/amd/amdgpu/vega10_ih.c

152

tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL);

sys/dev/drm/amd/amdgpu/vega10_ih.c

157

tmp = RREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL);

sys/dev/drm/amd/amdgpu/vega10_ih.c

47

u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL);

sys/dev/drm/amd/amdgpu/vega10_ih.c

64

u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL);

sys/dev/drm/amd/powerplay/hwmgr/smu10_hwmgr.c

1088

uint32_t reg_value = RREG32_SOC15(THM, 0, mmTHM_TCON_CUR_TMP);

sys/dev/drm/amd/powerplay/hwmgr/smu10_hwmgr.c

297

reg = RREG32_SOC15(PWR, 0, mmPWR_MISC_CNTL_STATUS);

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

3749

val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_PLANE0_CURRENTVID) &

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

908

data->mem_channels = (RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0) &

sys/dev/drm/amd/powerplay/hwmgr/vega10_thermal.c

106

REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_STATUS),

sys/dev/drm/amd/powerplay/hwmgr/vega10_thermal.c

134

REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),

sys/dev/drm/amd/powerplay/hwmgr/vega10_thermal.c

137

REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),

sys/dev/drm/amd/powerplay/hwmgr/vega10_thermal.c

143

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),

sys/dev/drm/amd/powerplay/hwmgr/vega10_thermal.c

146

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),

sys/dev/drm/amd/powerplay/hwmgr/vega10_thermal.c

163

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),

sys/dev/drm/amd/powerplay/hwmgr/vega10_thermal.c

167

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),

sys/dev/drm/amd/powerplay/hwmgr/vega10_thermal.c

268

duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),

sys/dev/drm/amd/powerplay/hwmgr/vega10_thermal.c

279

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),

sys/dev/drm/amd/powerplay/hwmgr/vega10_thermal.c

327

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),

sys/dev/drm/amd/powerplay/hwmgr/vega10_thermal.c

344

temp = RREG32_SOC15(THM, 0, mmCG_MULT_THERMAL_STATUS);

sys/dev/drm/amd/powerplay/hwmgr/vega10_thermal.c

382

val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);

sys/dev/drm/amd/powerplay/hwmgr/vega10_thermal.c

408

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),

sys/dev/drm/amd/powerplay/hwmgr/vega10_thermal.c

414

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),

sys/dev/drm/amd/powerplay/hwmgr/vega12_thermal.c

151

temp = RREG32_SOC15(THM, 0, mmCG_MULT_THERMAL_STATUS);

sys/dev/drm/amd/powerplay/hwmgr/vega12_thermal.c

188

val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);

sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c

2013

val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) &

sys/dev/drm/amd/powerplay/hwmgr/vega20_thermal.c

150

duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),

sys/dev/drm/amd/powerplay/hwmgr/vega20_thermal.c

161

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),

sys/dev/drm/amd/powerplay/hwmgr/vega20_thermal.c

204

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),

sys/dev/drm/amd/powerplay/hwmgr/vega20_thermal.c

221

temp = RREG32_SOC15(THM, 0, mmCG_MULT_THERMAL_STATUS);

sys/dev/drm/amd/powerplay/hwmgr/vega20_thermal.c

258

val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);

sys/dev/drm/amd/powerplay/hwmgr/vega20_thermal.c

95

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),

sys/dev/drm/amd/powerplay/hwmgr/vega20_thermal.c

98

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),

sys/dev/drm/amd/powerplay/smumgr/smu10_smumgr.c

58

return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);

sys/dev/drm/amd/powerplay/smumgr/smu10_smumgr.c

75

return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);

sys/dev/drm/amd/powerplay/smumgr/smu9_smumgr.c

154

return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);

sys/dev/drm/amd/powerplay/smumgr/smu9_smumgr.c

47

mp1_fw_flags = RREG32_SOC15(NBIF, 0, mmPCIE_DATA2);

sys/dev/drm/amd/powerplay/smumgr/smu9_smumgr.c

75

return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);

sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c

155

return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);

sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c

55

mp1_fw_flags = RREG32_SOC15(NBIF, 0, mmPCIE_DATA2);

sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c

80

return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);