sys/dev/drm/amd/amdgpu/amdgpu_cgs.c

67

return RREG32_SMC(index);

sys/dev/drm/amd/amdgpu/amdgpu_debugfs.c

400

value = RREG32_SMC(*pos);

sys/dev/drm/amd/amdgpu/ci_dpm.c

1022

tmp = RREG32_SMC(ixCG_THERMAL_INT);

sys/dev/drm/amd/amdgpu/ci_dpm.c

1030

tmp = RREG32_SMC(ixCG_THERMAL_CTRL);

sys/dev/drm/amd/amdgpu/ci_dpm.c

1044

u32 thermal_int = RREG32_SMC(ixCG_THERMAL_INT);

sys/dev/drm/amd/amdgpu/ci_dpm.c

1076

tmp = (RREG32_SMC(ixCG_FDO_CTRL2) & CG_FDO_CTRL2__FDO_PWM_MODE_MASK)

sys/dev/drm/amd/amdgpu/ci_dpm.c

1079

tmp = (RREG32_SMC(ixCG_FDO_CTRL2) & CG_FDO_CTRL2__TMIN_MASK)

sys/dev/drm/amd/amdgpu/ci_dpm.c

1085

tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TMIN_MASK;

sys/dev/drm/amd/amdgpu/ci_dpm.c

1089

tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__FDO_PWM_MODE_MASK;

sys/dev/drm/amd/amdgpu/ci_dpm.c

1110

duty100 = (RREG32_SMC(ixCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK)

sys/dev/drm/amd/amdgpu/ci_dpm.c

1155

tmp = (RREG32_SMC(ixCG_MULT_THERMAL_CTRL) & CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK)

sys/dev/drm/amd/amdgpu/ci_dpm.c

1226

duty100 = (RREG32_SMC(ixCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK)

sys/dev/drm/amd/amdgpu/ci_dpm.c

1228

duty = (RREG32_SMC(ixCG_THERMAL_STATUS) & CG_THERMAL_STATUS__FDO_PWM_DUTY_MASK)

sys/dev/drm/amd/amdgpu/ci_dpm.c

1262

duty100 = (RREG32_SMC(ixCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK)

sys/dev/drm/amd/amdgpu/ci_dpm.c

1272

tmp = RREG32_SMC(ixCG_FDO_CTRL0) & ~CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK;

sys/dev/drm/amd/amdgpu/ci_dpm.c

1326

tach_period = (RREG32_SMC(ixCG_TACH_STATUS) & CG_TACH_STATUS__TACH_PERIOD_MASK)

sys/dev/drm/amd/amdgpu/ci_dpm.c

1356

tmp = RREG32_SMC(ixCG_TACH_CTRL) & ~CG_TACH_CTRL__TARGET_PERIOD_MASK;

sys/dev/drm/amd/amdgpu/ci_dpm.c

1372

tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__FDO_PWM_MODE_MASK;

sys/dev/drm/amd/amdgpu/ci_dpm.c

1376

tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TMIN_MASK;

sys/dev/drm/amd/amdgpu/ci_dpm.c

1396

tmp = RREG32_SMC(ixCG_TACH_CTRL) & ~CG_TACH_CTRL__EDGE_PER_REV_MASK;

sys/dev/drm/amd/amdgpu/ci_dpm.c

1402

tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK;

sys/dev/drm/amd/amdgpu/ci_dpm.c

1562

tmp = RREG32_SMC(ixCG_THERMAL_CTRL);

sys/dev/drm/amd/amdgpu/ci_dpm.c

1568

tmp = RREG32_SMC(ixGENERAL_PWRMGT);

sys/dev/drm/amd/amdgpu/ci_dpm.c

1575

tmp = RREG32_SMC(ixGENERAL_PWRMGT);

sys/dev/drm/amd/amdgpu/ci_dpm.c

1686

tmp = RREG32_SMC(ixGENERAL_PWRMGT);

sys/dev/drm/amd/amdgpu/ci_dpm.c

1690

tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);

sys/dev/drm/amd/amdgpu/ci_dpm.c

1747

tmp = RREG32_SMC(ixGENERAL_PWRMGT);

sys/dev/drm/amd/amdgpu/ci_dpm.c

1751

tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);

sys/dev/drm/amd/amdgpu/ci_dpm.c

1774

u32 tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);

sys/dev/drm/amd/amdgpu/ci_dpm.c

1937

if (RREG32_SMC(ixFIRMWARE_FLAGS) & FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK)

sys/dev/drm/amd/amdgpu/ci_dpm.c

2007

RREG32_SMC(ixCG_SPLL_FUNC_CNTL);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2009

RREG32_SMC(ixCG_SPLL_FUNC_CNTL_2);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2011

RREG32_SMC(ixCG_SPLL_FUNC_CNTL_3);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2013

RREG32_SMC(ixCG_SPLL_FUNC_CNTL_4);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2015

RREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2017

RREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM_2);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2039

u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2050

u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2119

u32 tmp = RREG32_SMC(ixCG_DISPLAY_GAP_CNTL);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2158

tmp = RREG32_SMC(ixGENERAL_PWRMGT);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2163

tmp = RREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2167

tmp = RREG32_SMC(ixGENERAL_PWRMGT);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2182

u32 tmp = RREG32_SMC(ixCG_DISPLAY_GAP_CNTL);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2196

tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2214

tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2238

if (RREG32_SMC(ixRCU_UC_EVENTS) & RCU_UC_EVENTS__boot_seq_done_MASK)

sys/dev/drm/amd/amdgpu/ci_dpm.c

2624

tmp = (RREG32_SMC(ixSMC_SCRATCH9) & 0x0000ff00) >> 8;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4236

tmp = RREG32_SMC(ixDPM_TABLE_475);

sys/dev/drm/amd/amdgpu/ci_dpm.c

4276

tmp = RREG32_SMC(ixDPM_TABLE_475);

sys/dev/drm/amd/amdgpu/ci_dpm.c

4305

tmp = RREG32_SMC(ixDPM_TABLE_475);

sys/dev/drm/amd/amdgpu/ci_dpm.c

4373

tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX_1) &

sys/dev/drm/amd/amdgpu/ci_dpm.c

4393

tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &

sys/dev/drm/amd/amdgpu/ci_dpm.c

4413

tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &

sys/dev/drm/amd/amdgpu/ci_dpm.c

4431

tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &

sys/dev/drm/amd/amdgpu/ci_dpm.c

4447

tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &

sys/dev/drm/amd/amdgpu/ci_dpm.c

4463

tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX_1) &

sys/dev/drm/amd/amdgpu/ci_dpm.c

4940

u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT);

sys/dev/drm/amd/amdgpu/ci_dpm.c

5990

u32 tmp = RREG32_SMC(ixCNB_PWRMGT_CNTL);

sys/dev/drm/amd/amdgpu/ci_dpm.c

6214

temp = (RREG32_SMC(ixCG_MULT_THERMAL_STATUS) & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >>

sys/dev/drm/amd/amdgpu/ci_dpm.c

6459

cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT);

sys/dev/drm/amd/amdgpu/ci_dpm.c

6464

cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT);

sys/dev/drm/amd/amdgpu/ci_dpm.c

6476

cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT);

sys/dev/drm/amd/amdgpu/ci_dpm.c

6481

cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT);

sys/dev/drm/amd/amdgpu/ci_dpm.c

707

data = RREG32_SMC(config_regs->offset);

sys/dev/drm/amd/amdgpu/ci_smc.c

119

u32 tmp = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL);

sys/dev/drm/amd/amdgpu/ci_smc.c

127

u32 tmp = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL);

sys/dev/drm/amd/amdgpu/ci_smc.c

142

u32 tmp = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);

sys/dev/drm/amd/amdgpu/ci_smc.c

151

u32 tmp = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);

sys/dev/drm/amd/amdgpu/ci_smc.c

160

u32 clk = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);

sys/dev/drm/amd/amdgpu/ci_smc.c

161

u32 pc_c = RREG32_SMC(ixSMC_PC_C);

sys/dev/drm/amd/amdgpu/ci_smc.c

199

tmp = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);

sys/dev/drm/amd/amdgpu/cik.c

1311

tmp = RREG32_SMC(cntl_reg);

sys/dev/drm/amd/amdgpu/cik.c

1318

if (RREG32_SMC(status_reg) & CG_DCLK_STATUS__DCLK_STATUS_MASK)

sys/dev/drm/amd/amdgpu/cik.c

1353

if (RREG32_SMC(ixCG_ECLK_STATUS) & CG_ECLK_STATUS__ECLK_STATUS_MASK)

sys/dev/drm/amd/amdgpu/cik.c

1360

tmp = RREG32_SMC(ixCG_ECLK_CNTL);

sys/dev/drm/amd/amdgpu/cik.c

1367

if (RREG32_SMC(ixCG_ECLK_STATUS) & CG_ECLK_STATUS__ECLK_STATUS_MASK)

sys/dev/drm/amd/amdgpu/cik.c

1648

orig = data = RREG32_SMC(ixTHM_CLK_CNTL);

sys/dev/drm/amd/amdgpu/cik.c

1656

orig = data = RREG32_SMC(ixMISC_CLK_CTRL);

sys/dev/drm/amd/amdgpu/cik.c

1664

orig = data = RREG32_SMC(ixCG_CLKPIN_CNTL);

sys/dev/drm/amd/amdgpu/cik.c

1669

orig = data = RREG32_SMC(ixCG_CLKPIN_CNTL_2);

sys/dev/drm/amd/amdgpu/cik.c

1674

orig = data = RREG32_SMC(ixMPLL_BYPASSCLK_SEL);

sys/dev/drm/amd/amdgpu/cik.c

845

if (RREG32_SMC(ixGENERAL_PWRMGT) & GENERAL_PWRMGT__GPU_COUNTER_CLK_MASK)

sys/dev/drm/amd/amdgpu/cik.c

848

if (RREG32_SMC(ixCG_CLKPIN_CNTL) & CG_CLKPIN_CNTL__XTALIN_DIVIDE_MASK)

sys/dev/drm/amd/amdgpu/cik.c

905

rom_cntl = RREG32_SMC(ixROM_CNTL);

sys/dev/drm/amd/amdgpu/kv_dpm.c

2508

nbdpmconfig1 = RREG32_SMC(ixNB_DPM_CONFIG_1);

sys/dev/drm/amd/amdgpu/kv_dpm.c

2537

tmp = RREG32_SMC(ixCG_THERMAL_INT_CTRL);

sys/dev/drm/amd/amdgpu/kv_dpm.c

2871

(RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &

sys/dev/drm/amd/amdgpu/kv_dpm.c

2881

tmp = (RREG32_SMC(ixSMU_VOLTAGE_STATUS) &

sys/dev/drm/amd/amdgpu/kv_dpm.c

2956

temp = RREG32_SMC(0xC0300E0C);

sys/dev/drm/amd/amdgpu/kv_dpm.c

3150

cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT_CTRL);

sys/dev/drm/amd/amdgpu/kv_dpm.c

3155

cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT_CTRL);

sys/dev/drm/amd/amdgpu/kv_dpm.c

3167

cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT_CTRL);

sys/dev/drm/amd/amdgpu/kv_dpm.c

3172

cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT_CTRL);

sys/dev/drm/amd/amdgpu/kv_dpm.c

3288

(RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &

sys/dev/drm/amd/amdgpu/kv_dpm.c

427

data = RREG32_SMC(config_regs->offset);

sys/dev/drm/amd/amdgpu/kv_dpm.c

728

u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT);

sys/dev/drm/amd/amdgpu/kv_dpm.c

743

u32 sclk_pwrmgt_cntl = RREG32_SMC(ixSCLK_PWRMGT_CNTL);

sys/dev/drm/amd/amdgpu/kv_dpm.c

754

u32 sclk_pwrmgt_cntl = RREG32_SMC(ixSCLK_PWRMGT_CNTL);

sys/dev/drm/amd/amdgpu/kv_smc.c

64

*enable_mask = RREG32_SMC(ixSMC_SYSCON_MSG_ARG_0);

sys/dev/drm/amd/amdgpu/si_dpm.c

2849

data = RREG32_SMC(offset);

sys/dev/drm/amd/amdgpu/si_dpm.c

7512

cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);

sys/dev/drm/amd/amdgpu/si_dpm.c

7517

cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);

sys/dev/drm/amd/amdgpu/si_dpm.c

7529

cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);

sys/dev/drm/amd/amdgpu/si_dpm.c

7534

cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

709

if (!(RREG32_SMC(ixCURRENT_PG_STATUS) &

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

720

if (RREG32_SMC(ixCURRENT_PG_STATUS) &

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

825

if (RREG32_SMC(ixCURRENT_PG_STATUS) &

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1484

data = RREG32_SMC(ixCURRENT_PG_STATUS_APU);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1486

data = RREG32_SMC(ixCURRENT_PG_STATUS);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

370

(RREG32_SMC(ixCC_HARVEST_FUSES) & CC_HARVEST_FUSES__UVD_DISABLE_MASK))

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1686

u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);

sys/dev/drm/amd/amdgpu/vce_v3_0.c

374

tmp = (RREG32_SMC(ixVCE_HARVEST_FUSE_MACRO__ADDRESS) &

sys/dev/drm/amd/amdgpu/vce_v3_0.c

378

tmp = (RREG32_SMC(ixCC_HARVEST_FUSES) &

sys/dev/drm/amd/amdgpu/vce_v3_0.c

820

data = RREG32_SMC(ixCURRENT_PG_STATUS_APU);

sys/dev/drm/amd/amdgpu/vce_v3_0.c

822

data = RREG32_SMC(ixCURRENT_PG_STATUS);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

875

u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);

sys/dev/drm/amd/amdgpu/vi.c

1346

temp = data = RREG32_SMC(ixCGTT_ROM_CLK_CTRL0);

sys/dev/drm/amd/amdgpu/vi.c

1555

data = RREG32_SMC(ixCGTT_ROM_CLK_CTRL0);

sys/dev/drm/amd/amdgpu/vi.c

334

tmp = RREG32_SMC(ixCG_CLKPIN_CNTL_2);

sys/dev/drm/amd/amdgpu/vi.c

338

tmp = RREG32_SMC(ixCG_CLKPIN_CNTL);

sys/dev/drm/amd/amdgpu/vi.c

389

rom_cntl = RREG32_SMC(ixROM_CNTL);

sys/dev/drm/amd/amdgpu/vi.c

731

tmp = RREG32_SMC(cntl_reg);

sys/dev/drm/amd/amdgpu/vi.c

742

tmp = RREG32_SMC(status_reg);

sys/dev/drm/amd/amdgpu/vi.c

818

if (RREG32_SMC(reg_status) & status_mask)

sys/dev/drm/amd/amdgpu/vi.c

826

tmp = RREG32_SMC(reg_ctrl);

sys/dev/drm/amd/amdgpu/vi.c

832

if (RREG32_SMC(reg_status) & status_mask)

sys/dev/drm/amd/amdgpu/vi.c

897

return (RREG32_SMC(ATI_REV_ID_FUSE_MACRO__ADDRESS) & ATI_REV_ID_FUSE_MACRO__MASK)

sys/dev/drm/radeon/ci_dpm.c

1007

duty100 = (RREG32_SMC(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;

sys/dev/drm/radeon/ci_dpm.c

1051

tmp = (RREG32_SMC(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT;

sys/dev/drm/radeon/ci_dpm.c

1118

duty100 = (RREG32_SMC(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;

sys/dev/drm/radeon/ci_dpm.c

1119

duty = (RREG32_SMC(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT;

sys/dev/drm/radeon/ci_dpm.c

1151

duty100 = (RREG32_SMC(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;

sys/dev/drm/radeon/ci_dpm.c

1160

tmp = RREG32_SMC(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK;

sys/dev/drm/radeon/ci_dpm.c

1191

tmp = RREG32_SMC(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK;

sys/dev/drm/radeon/ci_dpm.c

1208

tach_period = (RREG32_SMC(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT;

sys/dev/drm/radeon/ci_dpm.c

1237

tmp = RREG32_SMC(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK;

sys/dev/drm/radeon/ci_dpm.c

1253

tmp = RREG32_SMC(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;

sys/dev/drm/radeon/ci_dpm.c

1257

tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TMIN_MASK;

sys/dev/drm/radeon/ci_dpm.c

1277

tmp = RREG32_SMC(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK;

sys/dev/drm/radeon/ci_dpm.c

1282

tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK;

sys/dev/drm/radeon/ci_dpm.c

1444

tmp = RREG32_SMC(CG_THERMAL_CTRL);

sys/dev/drm/radeon/ci_dpm.c

1450

tmp = RREG32_SMC(GENERAL_PWRMGT);

sys/dev/drm/radeon/ci_dpm.c

1457

tmp = RREG32_SMC(GENERAL_PWRMGT);

sys/dev/drm/radeon/ci_dpm.c

1567

tmp = RREG32_SMC(GENERAL_PWRMGT);

sys/dev/drm/radeon/ci_dpm.c

1571

tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);

sys/dev/drm/radeon/ci_dpm.c

1628

tmp = RREG32_SMC(GENERAL_PWRMGT);

sys/dev/drm/radeon/ci_dpm.c

1632

tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);

sys/dev/drm/radeon/ci_dpm.c

1655

u32 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);

sys/dev/drm/radeon/ci_dpm.c

1839

if (RREG32_SMC(FIRMWARE_FLAGS) & INTERRUPTS_ENABLED)

sys/dev/drm/radeon/ci_dpm.c

1909

RREG32_SMC(CG_SPLL_FUNC_CNTL);

sys/dev/drm/radeon/ci_dpm.c

1911

RREG32_SMC(CG_SPLL_FUNC_CNTL_2);

sys/dev/drm/radeon/ci_dpm.c

1913

RREG32_SMC(CG_SPLL_FUNC_CNTL_3);

sys/dev/drm/radeon/ci_dpm.c

1915

RREG32_SMC(CG_SPLL_FUNC_CNTL_4);

sys/dev/drm/radeon/ci_dpm.c

1917

RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM);

sys/dev/drm/radeon/ci_dpm.c

1919

RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM_2);

sys/dev/drm/radeon/ci_dpm.c

1941

u32 tmp = RREG32_SMC(GENERAL_PWRMGT);

sys/dev/drm/radeon/ci_dpm.c

1952

u32 tmp = RREG32_SMC(GENERAL_PWRMGT);

sys/dev/drm/radeon/ci_dpm.c

2021

u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL);

sys/dev/drm/radeon/ci_dpm.c

2060

tmp = RREG32_SMC(GENERAL_PWRMGT);

sys/dev/drm/radeon/ci_dpm.c

2065

tmp = RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM);

sys/dev/drm/radeon/ci_dpm.c

2069

tmp = RREG32_SMC(GENERAL_PWRMGT);

sys/dev/drm/radeon/ci_dpm.c

2082

u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL);

sys/dev/drm/radeon/ci_dpm.c

2095

tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);

sys/dev/drm/radeon/ci_dpm.c

2113

tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);

sys/dev/drm/radeon/ci_dpm.c

2133

if (RREG32_SMC(RCU_UC_EVENTS) & BOOT_SEQ_DONE)

sys/dev/drm/radeon/ci_dpm.c

2521

tmp = (RREG32_SMC(SMC_SCRATCH9) & 0x0000ff00) >> 8;

sys/dev/drm/radeon/ci_dpm.c

4124

tmp = RREG32_SMC(DPM_TABLE_475);

sys/dev/drm/radeon/ci_dpm.c

4162

tmp = RREG32_SMC(DPM_TABLE_475);

sys/dev/drm/radeon/ci_dpm.c

4192

tmp = RREG32_SMC(DPM_TABLE_475);

sys/dev/drm/radeon/ci_dpm.c

4259

tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX_1) &

sys/dev/drm/radeon/ci_dpm.c

4278

tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &

sys/dev/drm/radeon/ci_dpm.c

4297

tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &

sys/dev/drm/radeon/ci_dpm.c

4314

tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &

sys/dev/drm/radeon/ci_dpm.c

4329

tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &

sys/dev/drm/radeon/ci_dpm.c

4344

tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX_1) &

sys/dev/drm/radeon/ci_dpm.c

4825

u32 tmp = RREG32_SMC(GENERAL_PWRMGT);

sys/dev/drm/radeon/ci_dpm.c

576

data = RREG32_SMC(config_regs->offset);

sys/dev/drm/radeon/ci_dpm.c

5891

u32 tmp = RREG32_SMC(CNB_PWRMGT_CNTL);

sys/dev/drm/radeon/ci_dpm.c

920

tmp = RREG32_SMC(CG_THERMAL_INT);

sys/dev/drm/radeon/ci_dpm.c

928

tmp = RREG32_SMC(CG_THERMAL_CTRL);

sys/dev/drm/radeon/ci_dpm.c

943

u32 thermal_int = RREG32_SMC(CG_THERMAL_INT);

sys/dev/drm/radeon/ci_dpm.c

975

tmp = (RREG32_SMC(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT;

sys/dev/drm/radeon/ci_dpm.c

977

tmp = (RREG32_SMC(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT;

sys/dev/drm/radeon/ci_dpm.c

982

tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TMIN_MASK;

sys/dev/drm/radeon/ci_dpm.c

986

tmp = RREG32_SMC(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;

sys/dev/drm/radeon/ci_smc.c

116

u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);

sys/dev/drm/radeon/ci_smc.c

124

u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);

sys/dev/drm/radeon/ci_smc.c

139

u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);

sys/dev/drm/radeon/ci_smc.c

148

u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);

sys/dev/drm/radeon/ci_smc.c

157

u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);

sys/dev/drm/radeon/ci_smc.c

158

u32 pc_c = RREG32_SMC(SMC_PC_C);

sys/dev/drm/radeon/ci_smc.c

176

tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);

sys/dev/drm/radeon/cik.c

1705

if (RREG32_SMC(GENERAL_PWRMGT) & GPU_COUNTER_CLK)

sys/dev/drm/radeon/cik.c

1708

if (RREG32_SMC(CG_CLKPIN_CNTL) & XTALIN_DIVIDE)

sys/dev/drm/radeon/cik.c

198

temp = (RREG32_SMC(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >>

sys/dev/drm/radeon/cik.c

217

temp = RREG32_SMC(0xC0300E0C);

sys/dev/drm/radeon/cik.c

9453

tmp = RREG32_SMC(cntl_reg);

sys/dev/drm/radeon/cik.c

9459

if (RREG32_SMC(status_reg) & DCLK_STATUS)

sys/dev/drm/radeon/cik.c

9493

if (RREG32_SMC(CG_ECLK_STATUS) & ECLK_STATUS)

sys/dev/drm/radeon/cik.c

9500

tmp = RREG32_SMC(CG_ECLK_CNTL);

sys/dev/drm/radeon/cik.c

9506

if (RREG32_SMC(CG_ECLK_STATUS) & ECLK_STATUS)

sys/dev/drm/radeon/cik.c

9782

orig = data = RREG32_SMC(THM_CLK_CNTL);

sys/dev/drm/radeon/cik.c

9788

orig = data = RREG32_SMC(MISC_CLK_CTRL);

sys/dev/drm/radeon/cik.c

9794

orig = data = RREG32_SMC(CG_CLKPIN_CNTL);

sys/dev/drm/radeon/cik.c

9799

orig = data = RREG32_SMC(CG_CLKPIN_CNTL_2);

sys/dev/drm/radeon/cik.c

9804

orig = data = RREG32_SMC(MPLL_BYPASSCLK_SEL);

sys/dev/drm/radeon/kv_dpm.c

1173

thermal_int = RREG32_SMC(CG_THERMAL_INT_CTRL);

sys/dev/drm/radeon/kv_dpm.c

2437

nbdpmconfig1 = RREG32_SMC(NB_DPM_CONFIG_1);

sys/dev/drm/radeon/kv_dpm.c

2464

tmp = RREG32_SMC(CG_THERMAL_INT_CTRL);

sys/dev/drm/radeon/kv_dpm.c

2801

(RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_SCLK_INDEX_MASK) >>

sys/dev/drm/radeon/kv_dpm.c

2810

tmp = (RREG32_SMC(SMU_VOLTAGE_STATUS) & SMU_VOLTAGE_CURRENT_LEVEL_MASK) >>

sys/dev/drm/radeon/kv_dpm.c

2824

(RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_SCLK_INDEX_MASK) >>

sys/dev/drm/radeon/kv_dpm.c

295

data = RREG32_SMC(config_regs->offset);

sys/dev/drm/radeon/kv_dpm.c

642

u32 tmp = RREG32_SMC(GENERAL_PWRMGT);

sys/dev/drm/radeon/kv_dpm.c

657

u32 sclk_pwrmgt_cntl = RREG32_SMC(SCLK_PWRMGT_CNTL);

sys/dev/drm/radeon/kv_dpm.c

667

u32 sclk_pwrmgt_cntl = RREG32_SMC(SCLK_PWRMGT_CNTL);

sys/dev/drm/radeon/kv_smc.c

61

*enable_mask = RREG32_SMC(SMC_SYSCON_MSG_ARG_0);

sys/dev/drm/radeon/ni.c

892

u32 temp = RREG32_SMC(TN_CURRENT_GNB_TEMP) & 0x7ff;

sys/dev/drm/radeon/radeon.h

2583

uint32_t tmp_ = RREG32_SMC(reg); \

sys/dev/drm/radeon/si.c

7471

if ((RREG32_SMC(CG_VCEPLL_FUNC_CNTL) & mask) == mask)

sys/dev/drm/radeon/si_dpm.c

2751

data = RREG32_SMC(offset);

sys/dev/drm/radeon/si_smc.c

115

u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);

sys/dev/drm/radeon/si_smc.c

131

tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);

sys/dev/drm/radeon/si_smc.c

145

u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);

sys/dev/drm/radeon/si_smc.c

154

u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);

sys/dev/drm/radeon/si_smc.c

163

u32 rst = RREG32_SMC(SMC_SYSCON_RESET_CNTL);

sys/dev/drm/radeon/si_smc.c

164

u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);

sys/dev/drm/radeon/si_smc.c

202

tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);

sys/dev/drm/radeon/trinity_dpm.c

1013

u32 value = RREG32_SMC(SMU_SCLK_DPM_TTT);

sys/dev/drm/radeon/trinity_dpm.c

1023

u32 value = RREG32_SMC(SMU_SCLK_DPM_TT_CNTL);

sys/dev/drm/radeon/trinity_dpm.c

1033

u32 tp = RREG32_SMC(PM_TP);

sys/dev/drm/radeon/trinity_dpm.c

1042

value = RREG32_SMC(PM_I_CNTL_1);

sys/dev/drm/radeon/trinity_dpm.c

1185

(RREG32_SMC(CC_SMU_MISC_FUSES) & MinSClkDid_MASK) >> MinSClkDid_SHIFT;

sys/dev/drm/radeon/trinity_dpm.c

1196

nbpsconfig = RREG32_SMC(NB_PSTATE_CONFIG);

sys/dev/drm/radeon/trinity_dpm.c

1318

u32 svi_mode = (RREG32_SMC(PM_CONFIG) & SVI_Mode) ? 1 : 0;

sys/dev/drm/radeon/trinity_dpm.c

1647

(RREG32_SMC(GPU_CAC_AVRG_CNTL) & WINDOW_SIZE_MASK) >> WINDOW_SIZE_SHIFT;

sys/dev/drm/radeon/trinity_dpm.c

383

value = RREG32_SMC(GFX_POWER_GATING_CNTL);

sys/dev/drm/radeon/trinity_dpm.c

511

if (RREG32_SMC(CC_SMU_TST_EFUSE1_MISC) & RB_BACKEND_DISABLE_MASK)

sys/dev/drm/radeon/trinity_dpm.c

512

WREG32_SMC(SMU_SCRATCH_A, (RREG32_SMC(SMU_SCRATCH_A) | 0x01));

sys/dev/drm/radeon/trinity_dpm.c

527

value = RREG32_SMC(PM_I_CNTL_1);

sys/dev/drm/radeon/trinity_dpm.c

532

value = RREG32_SMC(SMU_S_PG_CNTL);

sys/dev/drm/radeon/trinity_dpm.c

537

value = RREG32_SMC(SMU_S_PG_CNTL);

sys/dev/drm/radeon/trinity_dpm.c

541

value = RREG32_SMC(PM_I_CNTL_1);

sys/dev/drm/radeon/trinity_dpm.c

601

value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix);

sys/dev/drm/radeon/trinity_dpm.c

611

value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_PG_CNTL + ix);

sys/dev/drm/radeon/trinity_dpm.c

623

value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix);

sys/dev/drm/radeon/trinity_dpm.c

635

value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix);

sys/dev/drm/radeon/trinity_dpm.c

648

value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix);

sys/dev/drm/radeon/trinity_dpm.c

653

value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix);

sys/dev/drm/radeon/trinity_dpm.c

665

value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_3 + ix);

sys/dev/drm/radeon/trinity_dpm.c

677

value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_3 + ix);

sys/dev/drm/radeon/trinity_dpm.c

689

value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix);

sys/dev/drm/radeon/trinity_dpm.c

701

value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix);

sys/dev/drm/radeon/trinity_dpm.c

713

value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_AT + ix);

sys/dev/drm/radeon/trinity_dpm.c

744

value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix);

sys/dev/drm/radeon/trinity_dpm.c

753

if (RREG32_SMC(SMU_SCLK_DPM_CNTL) & SCLK_DPM_EN(1))

sys/dev/drm/radeon/trinity_dpm.c

761

u32 value = RREG32_SMC(SMU_SCLK_DPM_CNTL);

sys/dev/drm/radeon/trinity_dpm.c

800

sclk_dpm_cntl = RREG32_SMC(SMU_SCLK_DPM_CNTL);

sys/dev/drm/radeon/trinity_dpm.c

890

u32 tp = RREG32_SMC(PM_TP);