sys/dev/drm/amd/amdgpu/amdgpu.h

1133

uint32_t tmp_ = RREG32_PLL(reg); \

sys/dev/drm/radeon/r100.c

2700

tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);

sys/dev/drm/radeon/r100.c

374

sclk_cntl = RREG32_PLL(SCLK_CNTL);

sys/dev/drm/radeon/r100.c

375

sclk_cntl2 = RREG32_PLL(SCLK_CNTL2);

sys/dev/drm/radeon/r100.c

377

sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL);

sys/dev/drm/radeon/r100.c

3893

tmp = RREG32_PLL(R_00000D_SCLK_CNTL);

sys/dev/drm/radeon/r300.c

1361

tmp = RREG32_PLL(R_00000D_SCLK_CNTL);

sys/dev/drm/radeon/r420.c

197

sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL);

sys/dev/drm/radeon/radeon.h

2576

uint32_t tmp_ = RREG32_PLL(reg); \

sys/dev/drm/radeon/radeon_clocks.c

118

p1pll->reference_div = RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;

sys/dev/drm/radeon/radeon_clocks.c

148

RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) &

sys/dev/drm/radeon/radeon_clocks.c

196

u32 tmp = RREG32_PLL(RADEON_PPLL_REF_DIV);

sys/dev/drm/radeon/radeon_clocks.c

212

RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) &

sys/dev/drm/radeon/radeon_clocks.c

238

RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;

sys/dev/drm/radeon/radeon_clocks.c

264

RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) &

sys/dev/drm/radeon/radeon_clocks.c

356

RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) &

sys/dev/drm/radeon/radeon_clocks.c

396

tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL);

sys/dev/drm/radeon/radeon_clocks.c

400

tmp = RREG32_PLL(RADEON_SCLK_CNTL);

sys/dev/drm/radeon/radeon_clocks.c

406

tmp = RREG32_PLL(RADEON_SPLL_CNTL);

sys/dev/drm/radeon/radeon_clocks.c

41

fb_div = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV);

sys/dev/drm/radeon/radeon_clocks.c

412

tmp = RREG32_PLL(RADEON_SPLL_CNTL);

sys/dev/drm/radeon/radeon_clocks.c

418

tmp = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV);

sys/dev/drm/radeon/radeon_clocks.c

424

tmp = RREG32_PLL(RADEON_SPLL_CNTL);

sys/dev/drm/radeon/radeon_clocks.c

432

tmp = RREG32_PLL(RADEON_SPLL_CNTL);

sys/dev/drm/radeon/radeon_clocks.c

438

tmp = RREG32_PLL(RADEON_SPLL_CNTL);

sys/dev/drm/radeon/radeon_clocks.c

444

tmp = RREG32_PLL(RADEON_SCLK_CNTL);

sys/dev/drm/radeon/radeon_clocks.c

465

tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL);

sys/dev/drm/radeon/radeon_clocks.c

47

RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & RADEON_M_SPLL_REF_DIV_MASK;

sys/dev/drm/radeon/radeon_clocks.c

478

tmp = RREG32_PLL(RADEON_SCLK_CNTL);

sys/dev/drm/radeon/radeon_clocks.c

496

tmp = RREG32_PLL(RADEON_SCLK_CNTL);

sys/dev/drm/radeon/radeon_clocks.c

517

tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);

sys/dev/drm/radeon/radeon_clocks.c

522

tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);

sys/dev/drm/radeon/radeon_clocks.c

527

tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);

sys/dev/drm/radeon/radeon_clocks.c

54

post_div = RREG32_PLL(RADEON_SCLK_CNTL) & RADEON_SCLK_SRC_SEL_MASK;

sys/dev/drm/radeon/radeon_clocks.c

543

tmp = RREG32_PLL(R300_SCLK_CNTL2);

sys/dev/drm/radeon/radeon_clocks.c

552

tmp = RREG32_PLL(RADEON_SCLK_CNTL);

sys/dev/drm/radeon/radeon_clocks.c

570

tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);

sys/dev/drm/radeon/radeon_clocks.c

575

tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);

sys/dev/drm/radeon/radeon_clocks.c

580

tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);

sys/dev/drm/radeon/radeon_clocks.c

596

tmp = RREG32_PLL(RADEON_MCLK_MISC);

sys/dev/drm/radeon/radeon_clocks.c

601

tmp = RREG32_PLL(RADEON_MCLK_CNTL);

sys/dev/drm/radeon/radeon_clocks.c

616

tmp = RREG32_PLL(RADEON_MCLK_CNTL);

sys/dev/drm/radeon/radeon_clocks.c

633

tmp = RREG32_PLL(RADEON_SCLK_CNTL);

sys/dev/drm/radeon/radeon_clocks.c

639

tmp = RREG32_PLL(R300_SCLK_CNTL2);

sys/dev/drm/radeon/radeon_clocks.c

646

tmp = RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);

sys/dev/drm/radeon/radeon_clocks.c

657

tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL);

sys/dev/drm/radeon/radeon_clocks.c

665

tmp = RREG32_PLL(RADEON_SCLK_CNTL);

sys/dev/drm/radeon/radeon_clocks.c

688

tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);

sys/dev/drm/radeon/radeon_clocks.c

709

tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);

sys/dev/drm/radeon/radeon_clocks.c

71

fb_div = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV);

sys/dev/drm/radeon/radeon_clocks.c

716

tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);

sys/dev/drm/radeon/radeon_clocks.c

728

tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);

sys/dev/drm/radeon/radeon_clocks.c

738

tmp = RREG32_PLL(RADEON_SCLK_CNTL);

sys/dev/drm/radeon/radeon_clocks.c

749

tmp = RREG32_PLL(RADEON_SCLK_CNTL);

sys/dev/drm/radeon/radeon_clocks.c

760

tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);

sys/dev/drm/radeon/radeon_clocks.c

764

tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);

sys/dev/drm/radeon/radeon_clocks.c

77

RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & RADEON_M_SPLL_REF_DIV_MASK;

sys/dev/drm/radeon/radeon_clocks.c

770

tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);

sys/dev/drm/radeon/radeon_clocks.c

788

tmp = RREG32_PLL(R300_SCLK_CNTL2);

sys/dev/drm/radeon/radeon_clocks.c

793

tmp = RREG32_PLL(RADEON_SCLK_CNTL);

sys/dev/drm/radeon/radeon_clocks.c

804

tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);

sys/dev/drm/radeon/radeon_clocks.c

808

tmp = RREG32_PLL(RADEON_MCLK_CNTL);

sys/dev/drm/radeon/radeon_clocks.c

815

tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);

sys/dev/drm/radeon/radeon_clocks.c

821

tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);

sys/dev/drm/radeon/radeon_clocks.c

838

tmp = RREG32_PLL(RADEON_SCLK_CNTL);

sys/dev/drm/radeon/radeon_clocks.c

84

post_div = RREG32_PLL(RADEON_MCLK_CNTL) & 0x7;

sys/dev/drm/radeon/radeon_clocks.c

869

tmp = RREG32_PLL(R300_SCLK_CNTL2);

sys/dev/drm/radeon/radeon_clocks.c

878

tmp = RREG32_PLL(RADEON_MCLK_CNTL);

sys/dev/drm/radeon/radeon_clocks.c

888

tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);

sys/dev/drm/radeon/radeon_clocks.c

894

tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);

sys/dev/drm/radeon/radeon_clocks.c

906

tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);

sys/dev/drm/radeon/radeon_combios.c

1143

ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);

sys/dev/drm/radeon/radeon_combios.c

1148

RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;

sys/dev/drm/radeon/radeon_combios.c

2981

val = RREG32_PLL(reg);

sys/dev/drm/radeon/radeon_combios.c

3060

(RREG32_PLL

sys/dev/drm/radeon/radeon_combios.c

3110

tmp = RREG32_PLL(addr);

sys/dev/drm/radeon/radeon_combios.c

3128

(RREG32_PLL

sys/dev/drm/radeon/radeon_combios.c

3136

if (RREG32_PLL

sys/dev/drm/radeon/radeon_combios.c

3144

RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);

sys/dev/drm/radeon/radeon_combios.c

3148

RREG32_PLL

sys/dev/drm/radeon/radeon_legacy_crtc.c

1006

RREG32_PLL(RADEON_PPLL_CNTL));

sys/dev/drm/radeon/radeon_legacy_crtc.c

221

RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);

sys/dev/drm/radeon/radeon_legacy_crtc.c

229

while (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);

sys/dev/drm/radeon/radeon_legacy_crtc.c

248

RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);

sys/dev/drm/radeon/radeon_legacy_crtc.c

256

while (RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);

sys/dev/drm/radeon/radeon_legacy_crtc.c

851

uint32_t pixclks_cntl = ((RREG32_PLL(RADEON_PIXCLKS_CNTL) &

sys/dev/drm/radeon/radeon_legacy_crtc.c

900

RREG32_PLL(RADEON_P2PLL_CNTL));

sys/dev/drm/radeon/radeon_legacy_crtc.c

919

pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);

sys/dev/drm/radeon/radeon_legacy_crtc.c

931

if ((pll_ref_div == (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) &&

sys/dev/drm/radeon/radeon_legacy_crtc.c

932

(pll_fb_post_div == (RREG32_PLL(RADEON_PPLL_DIV_3) &

sys/dev/drm/radeon/radeon_legacy_encoders.c

108

pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1583

pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);

sys/dev/drm/radeon/radeon_legacy_encoders.c

659

vclk_ecp_cntl = RREG32_PLL(RADEON_VCLK_ECP_CNTL);

sys/dev/drm/radeon/radeon_legacy_tv.c

283

save_pll_test = RREG32_PLL(RADEON_PLL_TEST_CNTL);

sys/dev/drm/radeon/rs600.c

247

dyn_pwrmgt_sclk_length = RREG32_PLL(DYN_PWRMGT_SCLK_LENGTH);

sys/dev/drm/radeon/rs600.c

264

dyn_sclk_vol_cntl = RREG32_PLL(DYN_SCLK_VOL_CNTL);

sys/dev/drm/radeon/rs600.c

276

hdp_dyn_cntl = RREG32_PLL(HDP_DYN_CNTL);

sys/dev/drm/radeon/rs600.c

284

mc_host_dyn_cntl = RREG32_PLL(MC_HOST_DYN_CNTL);

sys/dev/drm/radeon/rs600.c

291

dyn_backbias_cntl = RREG32_PLL(DYN_BACKBIAS_CNTL);

sys/dev/drm/radeon/rv515.c

504

RREG32_PLL(R_00000F_CP_DYN_CNTL) | S_00000F_CP_FORCEON(1));

sys/dev/drm/radeon/rv515.c

506

RREG32_PLL(R_000011_E2_DYN_CNTL) | S_000011_E2_FORCEON(1));

sys/dev/drm/radeon/rv515.c

508

RREG32_PLL(R_000013_IDCT_DYN_CNTL) | S_000013_IDCT_FORCEON(1));