sys/dev/drm/amd/amdgpu/amdgpu_ttm.c

1619

value = RREG32_NO_KIQ(mmMM_DATA);

sys/dev/drm/amd/amdgpu/amdgpu_ttm.c

2298

value = RREG32_NO_KIQ(mmMM_DATA);

sys/dev/drm/amd/amdgpu/amdgpu_virt.c

41

return RREG32_NO_KIQ(0xc040) == 0xffffffff;

sys/dev/drm/amd/amdgpu/gmc_v9_0.c

401

tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng);

sys/dev/drm/amd/amdgpu/gmc_v9_0.c

414

tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng);

sys/dev/drm/amd/amdgpu/mxgpu_ai.c

137

reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,

sys/dev/drm/amd/amdgpu/mxgpu_ai.c

179

RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,

sys/dev/drm/amd/amdgpu/mxgpu_ai.c

226

u32 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL));

sys/dev/drm/amd/amdgpu/mxgpu_ai.c

278

u32 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL));

sys/dev/drm/amd/amdgpu/mxgpu_ai.c

55

return RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,

sys/dev/drm/amd/amdgpu/mxgpu_ai.c

65

reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,

sys/dev/drm/amd/amdgpu/mxgpu_vi.c

324

reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);

sys/dev/drm/amd/amdgpu/mxgpu_vi.c

329

reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);

sys/dev/drm/amd/amdgpu/mxgpu_vi.c

338

reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);

sys/dev/drm/amd/amdgpu/mxgpu_vi.c

346

reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);

sys/dev/drm/amd/amdgpu/mxgpu_vi.c

357

reg = RREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW0);

sys/dev/drm/amd/amdgpu/mxgpu_vi.c

373

reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);

sys/dev/drm/amd/amdgpu/mxgpu_vi.c

378

reg = RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW0);

sys/dev/drm/amd/amdgpu/mxgpu_vi.c

394

reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);

sys/dev/drm/amd/amdgpu/mxgpu_vi.c

404

reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);

sys/dev/drm/amd/amdgpu/mxgpu_vi.c

503

u32 tmp = RREG32_NO_KIQ(mmMAILBOX_INT_CNTL);

sys/dev/drm/amd/amdgpu/mxgpu_vi.c

533

u32 tmp = RREG32_NO_KIQ(mmMAILBOX_INT_CNTL);

sys/dev/drm/amd/amdgpu/vega10_ih.c

215

tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL));

sys/dev/drm/amd/amdgpu/vi.c

116

r = RREG32_NO_KIQ(mmSMC_IND_DATA_11);