sys/dev/drm/amd/display/dc/dce/dce_abm.c

208

REG_WRITE(MASTER_COMM_DATA_REG1, rampingBoundary);

sys/dev/drm/amd/display/dc/dce/dce_abm.c

228

REG_WRITE(MASTER_COMM_DATA_REG1, frame_ramp);

sys/dev/drm/amd/display/dc/dce/dce_abm.c

244

REG_WRITE(BIOS_SCRATCH_2, s2);

sys/dev/drm/amd/display/dc/dce/dce_abm.c

256

REG_WRITE(DC_ABM1_HG_SAMPLE_RATE, 0x103);

sys/dev/drm/amd/display/dc/dce/dce_abm.c

257

REG_WRITE(DC_ABM1_HG_SAMPLE_RATE, 0x101);

sys/dev/drm/amd/display/dc/dce/dce_abm.c

258

REG_WRITE(DC_ABM1_LS_SAMPLE_RATE, 0x103);

sys/dev/drm/amd/display/dc/dce/dce_abm.c

259

REG_WRITE(DC_ABM1_LS_SAMPLE_RATE, 0x101);

sys/dev/drm/amd/display/dc/dce/dce_abm.c

260

REG_WRITE(BL1_PWM_BL_UPDATE_SAMPLE_RATE, 0x101);

sys/dev/drm/amd/display/dc/dce/dce_abm.c

356

REG_WRITE(BL_PWM_CNTL,

sys/dev/drm/amd/display/dc/dce/dce_abm.c

358

REG_WRITE(BL_PWM_CNTL2,

sys/dev/drm/amd/display/dc/dce/dce_abm.c

360

REG_WRITE(BL_PWM_PERIOD_CNTL,

sys/dev/drm/amd/display/dc/dce/dce_abm.c

370

REG_WRITE(BL_PWM_CNTL, 0xC000FA00);

sys/dev/drm/amd/display/dc/dce/dce_abm.c

371

REG_WRITE(BL_PWM_PERIOD_CNTL, 0x000C0FA0);

sys/dev/drm/amd/display/dc/dce/dce_abm.c

391

REG_WRITE(BIOS_SCRATCH_2, value);

sys/dev/drm/amd/display/dc/dce/dce_audio.c

569

REG_WRITE(AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS,

sys/dev/drm/amd/display/dc/dce/dce_aux.c

115

REG_WRITE(AUX_CONTROL, value);

sys/dev/drm/amd/display/dc/dce/dce_aux.c

129

REG_WRITE(AUX_CONTROL, value);

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

910

REG_WRITE(PHASE[inst], clock_kHz);

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

911

REG_WRITE(MODULO[inst], dp_dto_ref_kHz);

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

104

REG_WRITE(DMCU_IRAM_RD_CTRL, psr_state_offset);

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

334

REG_WRITE(DMCU_IRAM_RD_CTRL, dmcu_state_offset);

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

351

REG_WRITE(DC_DMCU_SCRATCH, 0);

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

361

REG_WRITE(DMCU_IRAM_RD_CTRL, dmcu_version_offset);

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

420

REG_WRITE(MASTER_COMM_DATA_REG1, 0xFFFF);

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

461

REG_WRITE(DMCU_IRAM_WR_CTRL, start_offset);

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

464

REG_WRITE(DMCU_IRAM_WR_DATA, src[count]);

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

503

REG_WRITE(DMCU_IRAM_RD_CTRL, psr_state_offset);

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

79

REG_WRITE(DMCU_IRAM_WR_CTRL, start_offset);

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

82

REG_WRITE(DMCU_IRAM_WR_DATA, src[count]);

sys/dev/drm/amd/display/dc/dce/dce_hwseq.c

83

REG_WRITE(CRTC_H_BLANK_START_END[pipe->stream_res.tg->inst], value);

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c

241

REG_WRITE(DP_DPHY_TRAINING_PATTERN_SEL, index);

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c

281

REG_WRITE(DP_DPHY_INTERNAL_CTRL, value);

sys/dev/drm/amd/display/dc/dce/dce_opp.c

294

REG_WRITE(FMT_TEMPORAL_DITHER_PATTERN_CONTROL, 0);

sys/dev/drm/amd/display/dc/dce/dce_opp.c

296

REG_WRITE(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX, 0);

sys/dev/drm/amd/display/dc/dce/dce_opp.c

298

REG_WRITE(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, 0);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

122

REG_WRITE(AFMT_GENERIC_0, *content++);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

123

REG_WRITE(AFMT_GENERIC_1, *content++);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

124

REG_WRITE(AFMT_GENERIC_2, *content++);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

125

REG_WRITE(AFMT_GENERIC_3, *content++);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

126

REG_WRITE(AFMT_GENERIC_4, *content++);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

127

REG_WRITE(AFMT_GENERIC_5, *content++);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

128

REG_WRITE(AFMT_GENERIC_6, *content++);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

129

REG_WRITE(AFMT_GENERIC_7, *content);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

449

REG_WRITE(DP_MSA_MISC, misc1); /* MSA_MISC1 */

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

743

REG_WRITE(AFMT_AVI_INFO0, content[0]);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

745

REG_WRITE(AFMT_AVI_INFO1, content[1]);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

747

REG_WRITE(AFMT_AVI_INFO2, content[2]);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

749

REG_WRITE(AFMT_AVI_INFO3, content[3]);

sys/dev/drm/amd/display/dc/dce/dce_transform.c

1184

REG_WRITE(REGAMMA_LUT_INDEX, 0);

sys/dev/drm/amd/display/dc/dce/dce_transform.c

1189

REG_WRITE(REGAMMA_LUT_DATA, rgb->red_reg);

sys/dev/drm/amd/display/dc/dce/dce_transform.c

1190

REG_WRITE(REGAMMA_LUT_DATA, rgb->green_reg);

sys/dev/drm/amd/display/dc/dce/dce_transform.c

1191

REG_WRITE(REGAMMA_LUT_DATA, rgb->blue_reg);

sys/dev/drm/amd/display/dc/dce/dce_transform.c

1192

REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_red_reg);

sys/dev/drm/amd/display/dc/dce/dce_transform.c

1193

REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_green_reg);

sys/dev/drm/amd/display/dc/dce/dce_transform.c

1194

REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_blue_reg);

sys/dev/drm/amd/display/dc/dce/dce_transform.c

232

REG_WRITE(DCFE_MEM_PWR_CTRL, power_ctl);

sys/dev/drm/amd/display/dc/dce/dce_transform.c

301

REG_WRITE(SCL_AUTOMATIC_MODE_CONTROL, 0);

sys/dev/drm/amd/display/dc/dce/dce_transform.c

336

REG_WRITE(SCL_F_SHARP_CONTROL, 0);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

196

REG_WRITE(DCHUBBUB_TEST_DEBUG_INDEX, hubbub->debug_test_index_pstate);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

271

REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, prog_wm_value);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

282

REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A, prog_wm_value);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

296

REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, prog_wm_value);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

309

REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, prog_wm_value);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

323

REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, prog_wm_value);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

334

REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, prog_wm_value);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

345

REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B, prog_wm_value);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

359

REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, prog_wm_value);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

372

REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, prog_wm_value);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

386

REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, prog_wm_value);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

397

REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, prog_wm_value);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

408

REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C, prog_wm_value);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

422

REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, prog_wm_value);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

435

REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, prog_wm_value);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

449

REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, prog_wm_value);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

460

REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, prog_wm_value);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

471

REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D, prog_wm_value);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

485

REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, prog_wm_value);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

498

REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, prog_wm_value);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

512

REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, prog_wm_value);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

130

REG_WRITE(HUBPREQ_DEBUG_DB, value);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1119

REG_WRITE(DIO_MEM_PWR_CTRL, 0);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1123

REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1125

REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

402

REG_WRITE(D1VGA_CONTROL, 0);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

403

REG_WRITE(D2VGA_CONTROL, 0);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

404

REG_WRITE(D3VGA_CONTROL, 0);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

405

REG_WRITE(D4VGA_CONTROL, 0);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

986

REG_WRITE(REFCLK_CNTL, 0);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

988

REG_WRITE(DIO_MEM_PWR_CTRL, 0);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

992

REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

994

REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.c

211

REG_WRITE(DP_DPHY_TRAINING_PATTERN_SEL, index);

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.c

246

REG_WRITE(DP_DPHY_INTERNAL_CTRL, value);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

1088

REG_WRITE(OTG_TEST_PATTERN_COLOR, 0);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

1091

REG_WRITE(OTG_TEST_PATTERN_CONTROL, 0);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

1102

REG_WRITE(OTG_TEST_PATTERN_CONTROL, 0);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

1103

REG_WRITE(OTG_TEST_PATTERN_COLOR, 0);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

1104

REG_WRITE(OTG_TEST_PATTERN_PARAMETERS, 0);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

1318

REG_WRITE(OTG_CRC_CNTL, 0);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

667

REG_WRITE(OTG_TRIGA_CNTL, 0);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

964

REG_WRITE(OTG_TEST_PATTERN_PARAMETERS, 0);

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

110

REG_WRITE(AFMT_GENERIC_0, *content++);

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

111

REG_WRITE(AFMT_GENERIC_1, *content++);

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

112

REG_WRITE(AFMT_GENERIC_2, *content++);

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

113

REG_WRITE(AFMT_GENERIC_3, *content++);

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

114

REG_WRITE(AFMT_GENERIC_4, *content++);

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

115

REG_WRITE(AFMT_GENERIC_5, *content++);

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

116

REG_WRITE(AFMT_GENERIC_6, *content++);

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

117

REG_WRITE(AFMT_GENERIC_7, *content);

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

411

REG_WRITE(DP_MSA_MISC, misc1); /* MSA_MISC1 */

sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c

146

REG_WRITE(AUX_CONTROL, value);

sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c

160

REG_WRITE(AUX_CONTROL, value);