REG_WR
REG_WR(sc, BCE_CTX_CTX_DATA, ctx_val);
REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_WRITE_REQ));
REG_WR(sc, BCE_CTX_DATA_ADR, offset);
REG_WR(sc, BCE_CTX_DATA, ctx_val);
REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
REG_WR(sc, BCE_EMAC_MDIO_COMM, val);
REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
REG_WR(sc, BCE_EMAC_MDIO_COMM, val1);
REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2);
REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2);
REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
REG_WR(sc, BCE_NVM_COMMAND, cmd);
REG_WR(sc, BCE_NVM_CFG1, flash->config1);
REG_WR(sc, BCE_NVM_CFG2, flash->config2);
REG_WR(sc, BCE_NVM_CFG3, flash->config3);
REG_WR(sc, BCE_NVM_WRITE1, flash->write1);
REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code);
REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code);
REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val);
REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val);
REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET);
REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET);
REG_WR(sc, BCE_CTX_COMMAND, val);
REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA0,
REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA1,
REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_CTRL,
REG_WR(sc, BCE_CTX_VIRT_ADDR, 0);
REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr);
REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
REG_WR(sc, BCE_EMAC_MAC_MATCH0, val);
REG_WR(sc, BCE_EMAC_MAC_MATCH1, val);
REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, BCE_MISC_ENABLE_CLR_DEFAULT);
REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS,
REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
REG_WR(sc, BCE_MISC_COMMAND, BCE_MISC_COMMAND_SW_RESET);
REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val);
REG_WR(sc, BCE_MISC_ECO_HW_CTL,
REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
REG_WR(sc, BCE_DMA_CONFIG, val);
REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val);
REG_WR(sc, BCE_MQ_CONFIG, val);
REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val);
REG_WR(sc, BCE_MQ_KNL_WIND_END, val);
REG_WR(sc, BCE_RV2P_CONFIG, val);
REG_WR(sc, BCE_TBDR_CONFIG, val);
REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val);
REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK);
REG_WR(sc, BCE_HC_STATUS_ADDR_L, BCE_ADDR_LO(sc->status_block_paddr));
REG_WR(sc, BCE_HC_STATUS_ADDR_H, BCE_ADDR_HI(sc->status_block_paddr));
REG_WR(sc, BCE_HC_STATISTICS_ADDR_L,
REG_WR(sc, BCE_HC_STATISTICS_ADDR_H,
REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
REG_WR(sc, BCE_HC_COMP_PROD_TRIP,
REG_WR(sc, BCE_HC_TX_TICKS,
REG_WR(sc, BCE_HC_RX_TICKS,
REG_WR(sc, BCE_HC_COM_TICKS,
REG_WR(sc, BCE_HC_CMD_TICKS,
REG_WR(sc, BCE_HC_STATS_TICKS, (sc->bce_stats_ticks & 0xffff00));
REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
REG_WR(sc, BCE_HC_MSIX_BIT_VECTOR, BCE_HC_MSIX_BIT_VECTOR_VAL);
REG_WR(sc, BCE_HC_CONFIG, val);
REG_WR(sc, base,
REG_WR(sc, base + BCE_HC_TX_QUICK_CONS_TRIP_OFF,
REG_WR(sc, base + BCE_HC_RX_QUICK_CONS_TRIP_OFF,
REG_WR(sc, base + BCE_HC_TX_TICKS_OFF,
REG_WR(sc, base + BCE_HC_RX_TICKS_OFF,
REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW);
REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val);
REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT);
REG_WR(rxr->sc, BCE_MQ_MAP_L2_5, val | BCE_MQ_MAP_L2_5_ARM);
REG_WR(rxr->sc, MB_GET_CID_ADDR(rxr->rx_cid) + BCE_L2MQ_RX_HOST_BSEQ,
REG_WR(sc, BCE_PCICFG_STATUS_BIT_SET_CMD,
REG_WR(sc, BCE_PCICFG_STATUS_BIT_CLEAR_CMD,
REG_WR(sc, BCE_EMAC_STATUS, BCE_EMAC_STATUS_LINK_CHANGE);
REG_WR(rxr->sc, MB_GET_CID_ADDR(rxr->rx_cid) + BCE_L2MQ_RX_HOST_BSEQ,
REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, (rxr->idx << 24) |
REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, (rxr->idx << 24) |
REG_WR(sc, BCE_HC_COMMAND, sc->hc_command | BCE_HC_COMMAND_COAL_NOW);
REG_WR(rxr->sc, BCE_PCICFG_INT_ACK_CMD, (rxr->idx << 24) |
REG_WR(sc, BCE_EMAC_RX_MTU_SIZE,
REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu);
REG_WR(sc, BCE_RLUP_RSS_CONFIG, 0);
REG_WR(sc, BCE_TSCH_TSS_CFG, 0);
REG_WR(sc, BCE_TSCH_TSS_CFG,
REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT);
REG_WR(txr->sc, MB_GET_CID_ADDR(txr->tx_cid) + BCE_L2CTX_TX_HOST_BSEQ,
REG_WR(sc, BCE_HC_COMMAND,
REG_WR(sc, BCE_HC_COMMAND,
REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4),
REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4),
REG_WR(sc, BCE_EMAC_RX_MODE, rx_mode);
REG_WR(sc, BCE_RPM_SORT_USER0, 0x0);
REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode);
REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode | BCE_RPM_SORT_USER0_ENA);
REG_WR(sc, BCE_PCICFG_MSI_CONTROL,
REG_WR(sc, BCE_PCICFG_MSI_CONTROL, msi_ctrl);
REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
REG_WR(sc, base + BCE_HC_TX_QUICK_CONS_TRIP_OFF,
REG_WR(sc, BCE_HC_TX_TICKS,
REG_WR(sc, base + BCE_HC_TX_TICKS_OFF,
REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
REG_WR(sc, base + BCE_HC_RX_QUICK_CONS_TRIP_OFF,
REG_WR(sc, BCE_HC_RX_TICKS,
REG_WR(sc, base + BCE_HC_RX_TICKS_OFF,
REG_WR(sc, BCE_PCI_MSIX_CONTROL, BCE_MSIX_MAX - 1);
REG_WR(sc, BCE_PCI_MSIX_TBL_OFF_BIR, BCE_PCI_GRC_WINDOW2_BASE);
REG_WR(sc, BCE_PCI_MSIX_PBA_OFF_BIT, BCE_PCI_GRC_WINDOW3_BASE);
REG_WR(sc, BCE_PCI_GRC_WINDOW_ADDR, BCE_PCI_GRC_WINDOW_ADDR_SEP_WIN);
REG_WR(sc, BCE_PCI_GRC_WINDOW2_ADDR, BCE_MSIX_TABLE_ADDR);
REG_WR(sc, BCE_PCI_GRC_WINDOW3_ADDR, BCE_MSIX_PBA_ADDR);
REG_WR(sc, BCE_RLUP_RSS_KEY(i), rss_key);
REG_WR(sc, BCE_RLUP_RSS_DATA, tbl);
REG_WR(sc, BCE_RLUP_RSS_COMMAND, (i >> 3) |
REG_WR(sc, BCE_RLUP_RSS_CONFIG,
#define BCE_SETBIT(sc, reg, x) REG_WR(sc, reg, (REG_RD(sc, reg) | (x)))
#define BCE_CLRBIT(sc, reg, x) REG_WR(sc, reg, (REG_RD(sc, reg) & ~(x)))