sys/dev/drm/amd/display/dc/dce/dce_abm.c

190

REG_WAIT(BL_PWM_GRP1_REG_LOCK,

sys/dev/drm/amd/display/dc/dce/dce_abm.c

219

REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT,

sys/dev/drm/amd/display/dc/dce/dce_abm.c

247

REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT,

sys/dev/drm/amd/display/dc/dce/dce_abm.c

303

REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,

sys/dev/drm/amd/display/dc/dce/dce_abm.c

321

REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,

sys/dev/drm/amd/display/dc/dce/dce_aux.c

120

REG_WAIT(AUX_CONTROL, AUX_RESET_DONE, 1,

sys/dev/drm/amd/display/dc/dce/dce_aux.c

131

REG_WAIT(AUX_CONTROL, AUX_RESET_DONE, 0,

sys/dev/drm/amd/display/dc/dce/dce_aux.c

245

REG_WAIT(AUX_SW_STATUS, AUX_SW_DONE, 0,

sys/dev/drm/amd/display/dc/dce/dce_aux.c

371

value = REG_WAIT(AUX_SW_STATUS, AUX_SW_DONE, 1,

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

101

REG_WAIT(DCI_MEM_PWR_STATUS, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10);

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

125

REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

222

REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

299

REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000);

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

331

REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10);

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

358

REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10);

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

377

REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800);

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

387

REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800);

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

417

REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800);

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

430

REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800);

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

459

REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10);

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

472

REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800);

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

482

REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800);

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

500

REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10);

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

531

REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

641

REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

686

REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000);

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

704

REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000);

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

77

REG_WAIT(DCI_MEM_PWR_STATUS, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10);

sys/dev/drm/amd/display/dc/dce/dce_mem_input.c

597

REG_WAIT(DMIF_BUFFER_CONTROL,

sys/dev/drm/amd/display/dc/dce/dce_mem_input.c

634

REG_WAIT(DMIF_BUFFER_CONTROL,

sys/dev/drm/amd/display/dc/dce/dce_opp.c

498

REG_WAIT(FMT_CONTROL, FMT_420_PIXEL_PHASE_LOCKED, 1, 10, 10);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

722

REG_WAIT(DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING,

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

89

REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT,

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

942

REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS,

sys/dev/drm/amd/display/dc/dce/dce_transform.c

201

REG_WAIT(DCFE_MEM_PWR_STATUS, SCL_COEFF_MEM_PWR_STATE, 0, 1, 10);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

60

REG_WAIT(DCHUBP_CNTL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

436

REG_WAIT(DOMAIN1_PG_STATUS,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

444

REG_WAIT(DOMAIN3_PG_STATUS,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

452

REG_WAIT(DOMAIN5_PG_STATUS,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

460

REG_WAIT(DOMAIN7_PG_STATUS,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

488

REG_WAIT(DOMAIN0_PG_STATUS,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

496

REG_WAIT(DOMAIN2_PG_STATUS,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

504

REG_WAIT(DOMAIN4_PG_STATUS,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

512

REG_WAIT(DOMAIN6_PG_STATUS,

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c

101

REG_WAIT(MPCC_STATUS[id],

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

428

REG_WAIT(OPTC_INPUT_CLOCK_CONTROL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

436

REG_WAIT(OTG_CLOCK_CONTROL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

496

REG_WAIT(OTG_CLOCK_CONTROL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

608

REG_WAIT(OTG_MASTER_UPDATE_LOCK,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

762

REG_WAIT(OTG_STATUS,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

768

REG_WAIT(OTG_STATUS,

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

630

REG_WAIT(DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING,

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

79

REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT,

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

802

REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS,

sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c

151

REG_WAIT(AUX_CONTROL, AUX_RESET_DONE, 1,

sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c

162

REG_WAIT(AUX_CONTROL, AUX_RESET_DONE, 0,

sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c

274

REG_WAIT(AUX_SW_STATUS, AUX_SW_DONE, 0,

sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c

405

value = REG_WAIT(AUX_SW_STATUS, AUX_SW_DONE, 1,