sys/dev/drm/amd/display/dc/dce/dce_aux.c

210

value = REG_UPDATE_4(AUX_SW_DATA,

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

172

REG_UPDATE_4(DMCU_INTERRUPT_TO_UC_EN_MASK,

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

591

REG_UPDATE_4(DMCU_INTERRUPT_TO_UC_EN_MASK,

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c

151

REG_UPDATE_4(DP_DPHY_CNTL,

sys/dev/drm/amd/display/dc/dce/dce_mem_input.c

497

REG_UPDATE_4(PRESCALE_GRPH_CONTROL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

148

REG_UPDATE_4(DCSURF_TILING_CONFIG,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

378

REG_UPDATE_4(DCSURF_SURFACE_CONTROL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

488

REG_UPDATE_4(DCSURF_SURFACE_CONTROL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.c

121

REG_UPDATE_4(DP_DPHY_CNTL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

1017

REG_UPDATE_4(OTG_TEST_PATTERN_CONTROL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

840

REG_UPDATE_4(OTG_V_TOTAL_CONTROL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

917

REG_UPDATE_4(OTG_TEST_PATTERN_CONTROL,

sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c

240

value = REG_UPDATE_4(AUX_SW_DATA,