sys/dev/drm/amd/display/dc/bios/bios_parser_helper.c

69

REG_UPDATE(BIOS_SCRATCH_6, S6_ACC_MODE, 1);

sys/dev/drm/amd/display/dc/bios/bios_parser_helper.c

78

REG_UPDATE(BIOS_SCRATCH_6, S6_CRITICAL_STATE, critial_state);

sys/dev/drm/amd/display/dc/dce/dce_abm.c

183

REG_UPDATE(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, backlight_16bit);

sys/dev/drm/amd/display/dc/dce/dce_abm.c

186

REG_UPDATE(BL_PWM_GRP1_REG_LOCK,

sys/dev/drm/amd/display/dc/dce/dce_abm.c

216

REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);

sys/dev/drm/amd/display/dc/dce/dce_abm.c

223

REG_UPDATE(BL1_PWM_USER_LEVEL, BL1_PWM_USER_LEVEL, backlight_17_bit);

sys/dev/drm/amd/display/dc/dce/dce_abm.c

231

REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MCP_BL_SET);

sys/dev/drm/amd/display/dc/dce/dce_abm.c

234

REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);

sys/dev/drm/amd/display/dc/dce/dce_abm.c

272

REG_UPDATE(BL1_PWM_CURRENT_ABM_LEVEL,

sys/dev/drm/amd/display/dc/dce/dce_abm.c

275

REG_UPDATE(BL1_PWM_TARGET_ABM_LEVEL,

sys/dev/drm/amd/display/dc/dce/dce_abm.c

278

REG_UPDATE(BL1_PWM_USER_LEVEL,

sys/dev/drm/amd/display/dc/dce/dce_abm.c

312

REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);

sys/dev/drm/amd/display/dc/dce/dce_abm.c

330

REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);

sys/dev/drm/amd/display/dc/dce/dce_abm.c

362

REG_UPDATE(LVTMA_PWRSEQ_REF_DIV,

sys/dev/drm/amd/display/dc/dce/dce_abm.c

394

REG_UPDATE(BL_PWM_CNTL, BL_PWM_EN, 1);

sys/dev/drm/amd/display/dc/dce/dce_abm.c

397

REG_UPDATE(BL_PWM_GRP1_REG_LOCK,

sys/dev/drm/amd/display/dc/dce/dce_audio.c

819

REG_UPDATE(DCCG_AUDIO_DTO0_MODULE,

sys/dev/drm/amd/display/dc/dce/dce_audio.c

823

REG_UPDATE(DCCG_AUDIO_DTO0_PHASE,

sys/dev/drm/amd/display/dc/dce/dce_audio.c

841

REG_UPDATE(DCCG_AUDIO_DTO_SOURCE,

sys/dev/drm/amd/display/dc/dce/dce_audio.c

844

REG_UPDATE(DCCG_AUDIO_DTO_SOURCE,

sys/dev/drm/amd/display/dc/dce/dce_audio.c

853

REG_UPDATE(DCCG_AUDIO_DTO1_MODULE,

sys/dev/drm/amd/display/dc/dce/dce_audio.c

857

REG_UPDATE(DCCG_AUDIO_DTO1_PHASE,

sys/dev/drm/amd/display/dc/dce/dce_audio.c

860

REG_UPDATE(DCCG_AUDIO_DTO_SOURCE,

sys/dev/drm/amd/display/dc/dce/dce_audio.c

903

REG_UPDATE(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES,

sys/dev/drm/amd/display/dc/dce/dce_aux.c

137

REG_UPDATE(AUX_ARB_CONTROL, AUX_SW_USE_AUX_REG_REQ, 1);

sys/dev/drm/amd/display/dc/dce/dce_aux.c

244

REG_UPDATE(AUX_INTERRUPT_CONTROL, AUX_SW_DONE_ACK, 1);

sys/dev/drm/amd/display/dc/dce/dce_aux.c

247

REG_UPDATE(AUX_SW_CONTROL, AUX_SW_GO, 1);

sys/dev/drm/amd/display/dc/dce/dce_aux.c

62

REG_UPDATE(AUX_ARB_CONTROL, AUX_SW_DONE_USING_AUX_REG, 1);

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

757

REG_UPDATE(RESYNC_CNTL,

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

770

REG_UPDATE(RESYNC_CNTL,

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

774

REG_UPDATE(RESYNC_CNTL,

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

778

REG_UPDATE(RESYNC_CNTL,

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

782

REG_UPDATE(RESYNC_CNTL,

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

831

REG_UPDATE(PIXCLK_RESYNC_CNTL,

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

914

REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1);

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

112

REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 0);

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

131

REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

134

REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

138

REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

181

REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

185

REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

189

REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

193

REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

210

REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

219

REG_UPDATE(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, 1);

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

260

REG_UPDATE(MASTER_COMM_CMD_REG,

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

264

REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

307

REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, PSR_SET_WAITLOOP);

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

310

REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

380

REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

384

REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

423

REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

427

REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

475

REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

479

REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

498

REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 1);

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

511

REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 0);

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

537

REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

540

REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

544

REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

600

REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

604

REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

608

REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

612

REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

629

REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

638

REG_UPDATE(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, 1);

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

679

REG_UPDATE(MASTER_COMM_CMD_REG,

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

683

REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

712

REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, PSR_SET_WAITLOOP);

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

715

REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

99

REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 1);

sys/dev/drm/amd/display/dc/dce/dce_hwseq.c

117

REG_UPDATE(BLND_CONTROL[blnd_inst],

sys/dev/drm/amd/display/dc/dce/dce_hwseq.c

132

REG_UPDATE(DC_MEM_GLOBAL_PWR_REQ_CNTL,

sys/dev/drm/amd/display/dc/dce/dce_hwseq.c

140

REG_UPDATE(DCFEV_CLOCK_CONTROL,

sys/dev/drm/amd/display/dc/dce/dce_hwseq.c

171

REG_UPDATE(PIXEL_RATE_CNTL[tg_inst],

sys/dev/drm/amd/display/dc/dce/dce_hwseq.c

181

REG_UPDATE(PIXEL_RATE_CNTL[tg_inst],

sys/dev/drm/amd/display/dc/dce/dce_hwseq.c

192

REG_UPDATE(PHYPLL_PIXEL_RATE_CNTL[tg_inst],

sys/dev/drm/amd/display/dc/dce/dce_hwseq.c

43

REG_UPDATE(DCFE_CLOCK_CONTROL[fe_inst],

sys/dev/drm/amd/display/dc/dce/dce_i2c_hw.c

327

REG_UPDATE(DC_I2C_ARBITRATION, DC_I2C_SW_DONE_USING_I2C_REG, 1);

sys/dev/drm/amd/display/dc/dce/dce_i2c_hw.c

343

REG_UPDATE(DC_I2C_CONTROL, DC_I2C_SW_STATUS_RESET, 1);

sys/dev/drm/amd/display/dc/dce/dce_i2c_hw.c

58

REG_UPDATE(DC_I2C_CONTROL, DC_I2C_GO, 1);

sys/dev/drm/amd/display/dc/dce/dce_ipp.c

134

REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, false);

sys/dev/drm/amd/display/dc/dce/dce_ipp.c

144

REG_UPDATE(PRESCALE_GRPH_CONTROL,

sys/dev/drm/amd/display/dc/dce/dce_ipp.c

160

REG_UPDATE(PRESCALE_GRPH_CONTROL,

sys/dev/drm/amd/display/dc/dce/dce_ipp.c

164

REG_UPDATE(INPUT_GAMMA_CONTROL,

sys/dev/drm/amd/display/dc/dce/dce_ipp.c

184

REG_UPDATE(DC_LUT_RW_MODE, DC_LUT_RW_MODE, 0);

sys/dev/drm/amd/display/dc/dce/dce_ipp.c

213

REG_UPDATE(PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);

sys/dev/drm/amd/display/dc/dce/dce_ipp.c

214

REG_UPDATE(INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);

sys/dev/drm/amd/display/dc/dce/dce_ipp.c

49

REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, true);

sys/dev/drm/amd/display/dc/dce/dce_ipp.c

53

REG_UPDATE(CUR_CONTROL, CURSOR_EN, position->enable);

sys/dev/drm/amd/display/dc/dce/dce_ipp.c

64

REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, false);

sys/dev/drm/amd/display/dc/dce/dce_ipp.c

75

REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, true);

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c

1314

REG_UPDATE(DP_MSE_SAT_UPDATE,

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c

1362

REG_UPDATE(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, field);

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c

140

REG_UPDATE(DP_DPHY_CNTL, DPHY_BYPASS, enable);

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c

161

REG_UPDATE(DP_DPHY_PRBS_CNTL, DPHY_PRBS_EN, 0);

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c

230

REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, complete);

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c

404

REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0);

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c

408

REG_UPDATE(DP_DPHY_HBR2_PATTERN_CONTROL,

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c

418

REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c

439

REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0x1FF);

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c

486

REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_ADVANCE, 1);

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c

517

REG_UPDATE(DP_DPHY_FAST_TRAINING,

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c

520

REG_UPDATE(DP_DPHY_FAST_TRAINING,

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c

531

REG_UPDATE(DP_DPHY_BS_SR_SWAP_CNTL, DPHY_LOAD_BS_COUNT, 0x5);

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c

561

REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, 0);

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c

573

REG_UPDATE(DIG_BE_CNTL, DIG_HPD_SELECT, hpd_source);

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c

884

REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 0);

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c

888

REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 1);

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c

893

REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 2);

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c

897

REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 3);

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c

901

REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 5);

sys/dev/drm/amd/display/dc/dce/dce_mem_input.c

150

REG_UPDATE(GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT,

sys/dev/drm/amd/display/dc/dce/dce_mem_input.c

169

REG_UPDATE(DPG_WATERMARK_MASK_CONTROL,

sys/dev/drm/amd/display/dc/dce/dce_mem_input.c

183

REG_UPDATE(DPG_WATERMARK_MASK_CONTROL,

sys/dev/drm/amd/display/dc/dce/dce_mem_input.c

202

REG_UPDATE(DPG_WATERMARK_MASK_CONTROL,

sys/dev/drm/amd/display/dc/dce/dce_mem_input.c

210

REG_UPDATE(DPG_PIPE_NB_PSTATE_CHANGE_CONTROL,

sys/dev/drm/amd/display/dc/dce/dce_mem_input.c

215

REG_UPDATE(DPG_WATERMARK_MASK_CONTROL,

sys/dev/drm/amd/display/dc/dce/dce_mem_input.c

223

REG_UPDATE(DPG_PIPE_LOW_POWER_CONTROL,

sys/dev/drm/amd/display/dc/dce/dce_mem_input.c

234

REG_UPDATE(DPG_WATERMARK_MASK_CONTROL,

sys/dev/drm/amd/display/dc/dce/dce_mem_input.c

252

REG_UPDATE(DPG_WATERMARK_MASK_CONTROL,

sys/dev/drm/amd/display/dc/dce/dce_mem_input.c

256

REG_UPDATE(DPG_PIPE_STUTTER_CONTROL2,

sys/dev/drm/amd/display/dc/dce/dce_mem_input.c

259

REG_UPDATE(DPG_PIPE_STUTTER_CONTROL,

sys/dev/drm/amd/display/dc/dce/dce_mem_input.c

514

REG_UPDATE(GRPH_ENABLE, GRPH_ENABLE, 1);

sys/dev/drm/amd/display/dc/dce/dce_mem_input.c

604

REG_UPDATE(DPG_PIPE_ARBITRATION_CONTROL1,

sys/dev/drm/amd/display/dc/dce/dce_mem_input.c

612

REG_UPDATE(MC_HUB_RDREQ_DMIF_LIMIT,

sys/dev/drm/amd/display/dc/dce/dce_mem_input.c

642

REG_UPDATE(MC_HUB_RDREQ_DMIF_LIMIT,

sys/dev/drm/amd/display/dc/dce/dce_mem_input.c

697

REG_UPDATE(GRPH_UPDATE, GRPH_UPDATE_LOCK, 1);

sys/dev/drm/amd/display/dc/dce/dce_mem_input.c

699

REG_UPDATE(

sys/dev/drm/amd/display/dc/dce/dce_mem_input.c

727

REG_UPDATE(GRPH_UPDATE, GRPH_UPDATE_LOCK, 0);

sys/dev/drm/amd/display/dc/dce/dce_opp.c

173

REG_UPDATE(FMT_BIT_DEPTH_CONTROL,

sys/dev/drm/amd/display/dc/dce/dce_opp.c

206

REG_UPDATE(FMT_DITHER_RAND_R_SEED,

sys/dev/drm/amd/display/dc/dce/dce_opp.c

209

REG_UPDATE(FMT_DITHER_RAND_G_SEED,

sys/dev/drm/amd/display/dc/dce/dce_opp.c

212

REG_UPDATE(FMT_DITHER_RAND_B_SEED,

sys/dev/drm/amd/display/dc/dce/dce_opp.c

302

REG_UPDATE(FMT_BIT_DEPTH_CONTROL,

sys/dev/drm/amd/display/dc/dce/dce_opp.c

311

REG_UPDATE(FMT_BIT_DEPTH_CONTROL,

sys/dev/drm/amd/display/dc/dce/dce_opp.c

441

REG_UPDATE(FMT_CONTROL,

sys/dev/drm/amd/display/dc/dce/dce_opp.c

445

REG_UPDATE(CONTROL,

sys/dev/drm/amd/display/dc/dce/dce_opp.c

494

REG_UPDATE(FMT_CONTROL,

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

1002

REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

101

REG_UPDATE(AFMT_VBI_PACKET_CONTROL,

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

1017

REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

1027

REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, value);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

1338

REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, channels);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

1360

REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

1385

REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

1388

REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

1391

REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

1394

REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

1397

REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

1400

REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, audio_clock_info.n_48khz);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

1414

REG_UPDATE(AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

142

REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

1446

REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

1455

REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

1458

REG_UPDATE(AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, 0);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

146

REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

1470

REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, !!enable);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

1489

REG_UPDATE(DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

1497

REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

150

REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

1518

REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

1528

REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, !mute);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

154

REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

1577

REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

1578

REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, !enable);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

158

REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

162

REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

166

REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

170

REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

295

REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

299

REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

307

REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

315

REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

318

REG_UPDATE(DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, 1);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

322

REG_UPDATE(DP_VID_TIMING, DP_VID_N_MUL, 1);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

326

REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

340

REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

344

REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

348

REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

353

REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

357

REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

516

REG_UPDATE(TMDS_CNTL, TMDS_PIXEL_ENCODING, 1);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

519

REG_UPDATE(TMDS_CNTL, TMDS_PIXEL_ENCODING, 0);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

522

REG_UPDATE(TMDS_CNTL, TMDS_COLOR_FORMAT, 0);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

526

REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 1);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

529

REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 0);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

532

REG_UPDATE(DIG_FE_CNTL, TMDS_COLOR_FORMAT, 0);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

577

REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

640

REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

642

REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

644

REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE,

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

647

REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

741

REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

751

REG_UPDATE(AFMT_AVI_INFO3, AFMT_AVI_INFO_VERSION,

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

758

REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE,

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

76

REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

780

REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

864

REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

865

REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

866

REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

877

REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

903

REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

927

REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

935

REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

954

REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, true);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

96

REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

983

REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

989

REG_UPDATE(DP_VID_N, DP_VID_N, n_vid);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

991

REG_UPDATE(DP_VID_M, DP_VID_M, m_vid);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

993

REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 1);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

998

REG_UPDATE(DIG_FE_CNTL, DIG_START, 1);

sys/dev/drm/amd/display/dc/dce/dce_transform.c

1148

REG_UPDATE(DCFE_MEM_PWR_CTRL,

sys/dev/drm/amd/display/dc/dce/dce_transform.c

1151

REG_UPDATE(DCFE_MEM_LIGHT_SLEEP_CNTL,

sys/dev/drm/amd/display/dc/dce/dce_transform.c

1181

REG_UPDATE(REGAMMA_LUT_WRITE_EN_MASK,

sys/dev/drm/amd/display/dc/dce/dce_transform.c

1202

REG_UPDATE(DCFE_MEM_PWR_CTRL,

sys/dev/drm/amd/display/dc/dce/dce_transform.c

1205

REG_UPDATE(DCFE_MEM_LIGHT_SLEEP_CNTL,

sys/dev/drm/amd/display/dc/dce/dce_transform.c

127

REG_UPDATE(SCL_MODE, SCL_MODE, 0);

sys/dev/drm/amd/display/dc/dce/dce_transform.c

136

REG_UPDATE(SCL_MODE, SCL_MODE, 1);

sys/dev/drm/amd/display/dc/dce/dce_transform.c

138

REG_UPDATE(SCL_MODE, SCL_MODE, 2);

sys/dev/drm/amd/display/dc/dce/dce_transform.c

141

REG_UPDATE(SCL_MODE, SCL_PSCL_EN, 1);

sys/dev/drm/amd/display/dc/dce/dce_transform.c

397

REG_UPDATE(SCL_UPDATE, SCL_COEF_UPDATE_COMPLETE, 1);

sys/dev/drm/amd/display/dc/dce/dce_transform.c

399

REG_UPDATE(LB_DATA_FORMAT, ALPHA_EN, data->lb_params.alpha_en);

sys/dev/drm/amd/display/dc/dce120/dce120_hw_sequencer.c

210

REG_UPDATE(DCHUB_AGP_BASE,

sys/dev/drm/amd/display/dc/dce120/dce120_hw_sequencer.c

213

REG_UPDATE(DCHUB_AGP_BOT,

sys/dev/drm/amd/display/dc/dce120/dce120_hw_sequencer.c

216

REG_UPDATE(DCHUB_AGP_TOP,

sys/dev/drm/amd/display/dc/dce120/dce120_hw_sequencer.c

221

REG_UPDATE(DCHUB_AGP_BASE,

sys/dev/drm/amd/display/dc/dce120/dce120_hw_sequencer.c

224

REG_UPDATE(DCHUB_AGP_BOT,

sys/dev/drm/amd/display/dc/dce120/dce120_hw_sequencer.c

227

REG_UPDATE(DCHUB_AGP_TOP,

sys/dev/drm/amd/display/dc/dce120/dce120_hw_sequencer.c

232

REG_UPDATE(DCHUB_AGP_BASE,

sys/dev/drm/amd/display/dc/dce120/dce120_hw_sequencer.c

235

REG_UPDATE(DCHUB_AGP_BOT,

sys/dev/drm/amd/display/dc/dce120/dce120_hw_sequencer.c

238

REG_UPDATE(DCHUB_AGP_TOP,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c

289

REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, 3);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c

290

REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, 1);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c

292

REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, 2);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c

293

REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, 0);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c

399

REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c

420

REG_UPDATE(CURSOR_CONTROL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c

422

REG_UPDATE(CURSOR0_CONTROL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c

439

REG_UPDATE(CURSOR0_COLOR0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c

441

REG_UPDATE(CURSOR0_COLOR1,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c

471

REG_UPDATE(CURSOR0_CONTROL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c

483

REG_UPDATE(CURSOR0_FP_SCALE_BIAS, CUR0_FP_BIAS, attr->bias);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c

484

REG_UPDATE(CURSOR0_FP_SCALE_BIAS, CUR0_FP_SCALE, attr->scale);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c

501

REG_UPDATE(DPP_CONTROL, DPP_CLOCK_ENABLE, 1);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c

503

REG_UPDATE(DPP_CONTROL, DPP_CLOCK_ENABLE, 0);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

385

REG_UPDATE(CM_RGAM_LUT_WRITE_EN_MASK,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

387

REG_UPDATE(CM_RGAM_LUT_WRITE_EN_MASK,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

618

REG_UPDATE(CM_CMOUT_CONTROL, CM_CMOUT_ROUND_TRUNC_MODE, 8);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

619

REG_UPDATE(CM_CONTROL, CM_BYPASS_EN, 0);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

632

REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 0);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

635

REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 1);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

638

REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 2);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

653

REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 3);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

655

REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 4);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

689

REG_UPDATE(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_HOST_EN, 0);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

690

REG_UPDATE(CM_DGAM_LUT_WRITE_EN_MASK,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

692

REG_UPDATE(CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_LUT_WRITE_SEL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

795

REG_UPDATE(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_SEL, 0);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

797

REG_UPDATE(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_SEL, 1);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

799

REG_UPDATE(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_RW_MODE, 0);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

801

REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, 0);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

803

REG_UPDATE(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_WRITE_EN_MASK, 7);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

811

REG_UPDATE(CM_IGAM_LUT_RW_INDEX, CM_IGAM_LUT_RW_INDEX, 0);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

826

REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, rama_occupied ? 3 : 2);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

836

REG_UPDATE(CM_HDR_MULT_COEF, CM_HDR_MULT_COEF, multiplier);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c

526

REG_UPDATE(SCL_MODE, DSCL_MODE, dscl_mode);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c

682

REG_UPDATE(SCL_MODE, DSCL_MODE, dscl_mode);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

518

REG_UPDATE(DCHUBBUB_ARB_SAT_LEVEL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

520

REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

547

REG_UPDATE(DCHUBBUB_SDPIF_FB_TOP,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

550

REG_UPDATE(DCHUBBUB_SDPIF_FB_BASE,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

553

REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

556

REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

559

REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

566

REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

569

REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

572

REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

578

REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

581

REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

584

REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

607

REG_UPDATE(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

615

REG_UPDATE(DCHUBBUB_SOFT_RESET,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

92

REG_UPDATE(DCHUBBUB_ARB_DRAM_STATE_CNTL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

1062

REG_UPDATE(CURSOR_SURFACE_ADDRESS_HIGH,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

1064

REG_UPDATE(CURSOR_SURFACE_ADDRESS,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

107

REG_UPDATE(DCHUBP_CNTL, HUBP_BLANK_EN, blank_en);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

1143

REG_UPDATE(CURSOR_CONTROL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

1164

REG_UPDATE(HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, clk_enable);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

1171

REG_UPDATE(DCHUBP_CNTL, HUBP_VTG_SEL, otg_inst);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

253

REG_UPDATE(DCSURF_SURFACE_CONFIG,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

257

REG_UPDATE(DCSURF_SURFACE_CONFIG,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

262

REG_UPDATE(DCSURF_SURFACE_CONFIG,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

268

REG_UPDATE(DCSURF_SURFACE_CONFIG,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

272

REG_UPDATE(DCSURF_SURFACE_CONFIG,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

277

REG_UPDATE(DCSURF_SURFACE_CONFIG,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

282

REG_UPDATE(DCSURF_SURFACE_CONFIG,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

286

REG_UPDATE(DCSURF_SURFACE_CONFIG,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

290

REG_UPDATE(DCSURF_SURFACE_CONFIG,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

294

REG_UPDATE(DCSURF_SURFACE_CONFIG,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

298

REG_UPDATE(DCSURF_SURFACE_CONFIG,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

318

REG_UPDATE(DCSURF_FLIP_CONTROL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

323

REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0x1);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

324

REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x1);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

328

REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0x0);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

329

REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x0);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

518

REG_UPDATE(HUBPRET_CONTROL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

74

REG_UPDATE(DCHUBP_CNTL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

77

REG_UPDATE(CURSOR_CONTROL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

86

REG_UPDATE(DCHUBP_CNTL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1127

REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

373

REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

374

REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

375

REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

376

REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

379

REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

380

REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

381

REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

382

REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

414

REG_UPDATE(VGA_TEST_CONTROL, VGA_TEST_ENABLE, 1);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

415

REG_UPDATE(VGA_TEST_CONTROL, VGA_TEST_RENDER_START, 1);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

433

REG_UPDATE(DOMAIN1_PG_CONFIG,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

441

REG_UPDATE(DOMAIN3_PG_CONFIG,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

449

REG_UPDATE(DOMAIN5_PG_CONFIG,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

457

REG_UPDATE(DOMAIN7_PG_CONFIG,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

485

REG_UPDATE(DOMAIN0_PG_CONFIG,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

493

REG_UPDATE(DOMAIN2_PG_CONFIG,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

501

REG_UPDATE(DOMAIN4_PG_CONFIG,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

509

REG_UPDATE(DOMAIN6_PG_CONFIG,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

987

REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

996

REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.c

110

REG_UPDATE(DP_DPHY_CNTL, DPHY_BYPASS, enable);

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.c

1233

REG_UPDATE(DP_MSE_SAT_UPDATE,

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.c

1281

REG_UPDATE(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, field);

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.c

131

REG_UPDATE(DP_DPHY_PRBS_CNTL, DPHY_PRBS_EN, 0);

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.c

200

REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, complete);

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.c

371

REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0);

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.c

375

REG_UPDATE(DP_DPHY_HBR2_PATTERN_CONTROL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.c

385

REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.c

406

REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0x1FF);

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.c

452

REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_ADVANCE, 1);

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.c

461

REG_UPDATE(DP_DPHY_FAST_TRAINING,

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.c

464

REG_UPDATE(DP_DPHY_FAST_TRAINING,

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.c

475

REG_UPDATE(DP_DPHY_BS_SR_SWAP_CNTL, DPHY_LOAD_BS_COUNT, 0x5);

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.c

505

REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, 0);

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.c

517

REG_UPDATE(DIG_BE_CNTL, DIG_HPD_SELECT, hpd_source);

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.c

830

REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 0);

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.c

834

REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 1);

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.c

839

REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 2);

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.c

843

REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 3);

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.c

847

REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 5);

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c

210

REG_UPDATE(MPCC_CONTROL[mpcc_id], MPCC_MODE, MPCC_BLEND_MODE_TOP_BOT_BLENDING);

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c

214

REG_UPDATE(MPCC_CONTROL[mpcc_id], MPCC_MODE, MPCC_BLEND_MODE_TOP_LAYER_PASSTHROUGH);

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c

223

REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, mpcc_id);

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c

234

REG_UPDATE(MPCC_CONTROL[temp_mpcc->mpcc_id],

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c

279

REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, tree->opp_list->mpcc_id);

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c

283

REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, 0xf);

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c

303

REG_UPDATE(MPCC_CONTROL[temp_mpcc->mpcc_id],

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c

363

REG_UPDATE(MUX[opp_id], MPC_OUT_MUX, 0xf);

sys/dev/drm/amd/display/dc/dcn10/dcn10_opp.c

166

REG_UPDATE(FMT_CONTROL, FMT_PIXEL_ENCODING, 0);

sys/dev/drm/amd/display/dc/dcn10/dcn10_opp.c

169

REG_UPDATE(FMT_CONTROL, FMT_PIXEL_ENCODING, 1);

sys/dev/drm/amd/display/dc/dcn10/dcn10_opp.c

172

REG_UPDATE(FMT_CONTROL, FMT_PIXEL_ENCODING, 2);

sys/dev/drm/amd/display/dc/dcn10/dcn10_opp.c

284

REG_UPDATE(FMT_MAP420_MEMORY_CONTROL, FMT_MAP420MEM_PWR_FORCE, 0);

sys/dev/drm/amd/display/dc/dcn10/dcn10_opp.c

318

REG_UPDATE(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, 0);

sys/dev/drm/amd/display/dc/dcn10/dcn10_opp.c

320

REG_UPDATE(OPPBUF_CONTROL, OPPBUF_ACTIVE_WIDTH, active_width);

sys/dev/drm/amd/display/dc/dcn10/dcn10_opp.c

328

REG_UPDATE(OPPBUF_3D_PARAMETERS_0, OPPBUF_3D_VACT_SPACE2_SIZE, space2_size);

sys/dev/drm/amd/display/dc/dcn10/dcn10_opp.c

330

REG_UPDATE(OPPBUF_3D_PARAMETERS_0, OPPBUF_3D_VACT_SPACE1_SIZE, space1_size);

sys/dev/drm/amd/display/dc/dcn10/dcn10_opp.c

351

REG_UPDATE(OPPBUF_CONTROL, OPPBUF_ACTIVE_WIDTH, oppbuf->active_width);

sys/dev/drm/amd/display/dc/dcn10/dcn10_opp.c

359

REG_UPDATE(OPPBUF_CONTROL, OPPBUF_DISPLAY_SEGMENTATION, oppbuf->mso_segmentation);

sys/dev/drm/amd/display/dc/dcn10/dcn10_opp.c

362

REG_UPDATE(OPPBUF_CONTROL, OPPBUF_OVERLAP_PIXEL_NUM, oppbuf->mso_overlap_pixel_num);

sys/dev/drm/amd/display/dc/dcn10/dcn10_opp.c

367

REG_UPDATE(OPPBUF_CONTROL, OPPBUF_PIXEL_REPETITION, oppbuf->pixel_repetition);

sys/dev/drm/amd/display/dc/dcn10/dcn10_opp.c

377

REG_UPDATE(OPP_PIPE_CONTROL, OPP_PIPE_CLOCK_EN, regval);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

1149

REG_UPDATE(OTG_STEREO_CONTROL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

1154

REG_UPDATE(OTG_STEREO_CONTROL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

1277

REG_UPDATE(OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, 1);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

232

REG_UPDATE(OTG_H_SYNC_A_CNTL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

288

REG_UPDATE(OTG_V_SYNC_A_CNTL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

305

REG_UPDATE(OTG_INTERLACE_CONTROL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

311

REG_UPDATE(OTG_INTERLACE_CONTROL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

316

REG_UPDATE(CONTROL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

343

REG_UPDATE(OTG_H_TIMING_CNTL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

354

REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

465

REG_UPDATE(OPTC_DATA_SOURCE_SELECT,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

469

REG_UPDATE(CONTROL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

492

REG_UPDATE(CONTROL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

1177

REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, channels);

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

1189

REG_UPDATE(HDMI_AUDIO_PACKET_CONTROL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

1193

REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

1218

REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz);

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

122

REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

1221

REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz);

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

1224

REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz);

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

1227

REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz);

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

1230

REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz);

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

1233

REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, audio_clock_info.n_48khz);

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

1249

REG_UPDATE(AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

126

REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

1283

REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

1292

REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

1295

REG_UPDATE(AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, 0);

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

130

REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

1307

REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, !!enable);

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

1326

REG_UPDATE(DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1);

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

1334

REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

134

REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

1356

REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

1366

REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, !mute);

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

138

REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

1415

REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst);

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

1416

REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, !enable);

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

142

REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

146

REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

150

REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

289

REG_UPDATE(DP_VID_TIMING, DP_VID_N_MUL, 1);

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

468

REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 1);

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

471

REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 0);

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

474

REG_UPDATE(DIG_FE_CNTL, TMDS_COLOR_FORMAT, 0);

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

511

REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

573

REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

575

REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

577

REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE,

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

580

REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0);

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

642

REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1);

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

67

REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

720

REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid);

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

721

REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid);

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

722

REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid);

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

734

REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

761

REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

787

REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2);

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

795

REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

814

REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, true);

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

843

REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0);

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

849

REG_UPDATE(DP_VID_N, DP_VID_N, n_vid);

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

851

REG_UPDATE(DP_VID_M, DP_VID_M, m_vid);

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

853

REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 1);

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

858

REG_UPDATE(DIG_FE_CNTL, DIG_START, 1);

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

86

REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1);

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

862

REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0);

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

877

REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true);

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

887

REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, value);

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

90

REG_UPDATE(AFMT_VBI_PACKET_CONTROL,

sys/dev/drm/amd/display/dc/gpio/hw_ddc.c

143

REG_UPDATE(gpio.MASK_reg,

sys/dev/drm/amd/display/dc/gpio/hw_gpio.c

107

REG_UPDATE(A_reg, A, value);

sys/dev/drm/amd/display/dc/gpio/hw_gpio.c

114

REG_UPDATE(EN_reg, EN, ~value);

sys/dev/drm/amd/display/dc/gpio/hw_gpio.c

151

REG_UPDATE(EN_reg, EN, 0);

sys/dev/drm/amd/display/dc/gpio/hw_gpio.c

152

REG_UPDATE(MASK_reg, MASK, 1);

sys/dev/drm/amd/display/dc/gpio/hw_gpio.c

157

REG_UPDATE(A_reg, A, 0);

sys/dev/drm/amd/display/dc/gpio/hw_gpio.c

158

REG_UPDATE(MASK_reg, MASK, 1);

sys/dev/drm/amd/display/dc/gpio/hw_gpio.c

163

REG_UPDATE(A_reg, A, 0);

sys/dev/drm/amd/display/dc/gpio/hw_gpio.c

164

REG_UPDATE(MASK_reg, MASK, 1);

sys/dev/drm/amd/display/dc/gpio/hw_gpio.c

168

REG_UPDATE(MASK_reg, MASK, 0);

sys/dev/drm/amd/display/dc/gpio/hw_gpio.c

172

REG_UPDATE(MASK_reg, MASK, 0);

sys/dev/drm/amd/display/dc/gpio/hw_gpio.c

54

REG_UPDATE(MASK_reg, MASK, gpio->store.mask);

sys/dev/drm/amd/display/dc/gpio/hw_gpio.c

55

REG_UPDATE(A_reg, A, gpio->store.a);

sys/dev/drm/amd/display/dc/gpio/hw_gpio.c

56

REG_UPDATE(EN_reg, EN, gpio->store.en);

sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c

168

REG_UPDATE(AUX_ARB_CONTROL, AUX_SW_USE_AUX_REG_REQ, 1);

sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c

273

REG_UPDATE(AUX_INTERRUPT_CONTROL, AUX_SW_DONE_ACK, 1);

sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c

276

REG_UPDATE(AUX_SW_CONTROL, AUX_SW_GO, 1);

sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c

78

REG_UPDATE(AUX_ARB_CONTROL, AUX_SW_DONE_USING_AUX_REG, 1);

sys/dev/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c

123

REG_UPDATE(DC_I2C_ARBITRATION, DC_I2C_SW_DONE_USING_I2C_REG, 1);

sys/dev/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c

139

REG_UPDATE(DC_I2C_CONTROL, DC_I2C_SW_STATUS_RESET, 1);

sys/dev/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c

358

REG_UPDATE(DC_I2C_CONTROL, DC_I2C_GO, 1);

sys/dev/drm/amd/display/dc/inc/reg_helper.h

384

{ uint32_t val = REG_UPDATE(reg, field, value1); \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

389

{ uint32_t val = REG_UPDATE(reg, f1, v1); \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

393

{ uint32_t val = REG_UPDATE(reg, f1, v1); \