sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
337
value = REG_SET_FIELD(value, RLC_CP_SCHEDULERS, scheduler1,
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
365
data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control,
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
379
data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1);
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
448
data = REG_SET_FIELD(data, SDMA1_GFX_CONTEXT_CNTL,
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
453
data = REG_SET_FIELD(data, SDMA0_GFX_CONTEXT_CNTL,
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
458
data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL,
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
479
data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL,
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
748
data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
750
data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
752
data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
426
value = REG_SET_FIELD(value, RLC_CP_SCHEDULERS, scheduler1,
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
441
data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control,
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
486
REG_SET_FIELD(m->cp_hqd_eop_rptr,
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
489
data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1);
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
560
data = REG_SET_FIELD(data, SDMA0_GFX_CONTEXT_CNTL,
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
567
data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL,
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
596
data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL,
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
936
data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
938
data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
940
data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
sys/dev/drm/amd/amdgpu/cik_sdma.c
375
f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
sys/dev/drm/amd/amdgpu/cik_sdma.c
384
f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
sys/dev/drm/amd/amdgpu/cz_ih.c
119
interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
sys/dev/drm/amd/amdgpu/cz_ih.c
121
interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
sys/dev/drm/amd/amdgpu/cz_ih.c
128
ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 1);
sys/dev/drm/amd/amdgpu/cz_ih.c
129
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
sys/dev/drm/amd/amdgpu/cz_ih.c
130
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);
sys/dev/drm/amd/amdgpu/cz_ih.c
133
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1);
sys/dev/drm/amd/amdgpu/cz_ih.c
148
ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, MC_VMID, 0);
sys/dev/drm/amd/amdgpu/cz_ih.c
151
ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, RPTR_REARM, 1);
sys/dev/drm/amd/amdgpu/cz_ih.c
195
wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
sys/dev/drm/amd/amdgpu/cz_ih.c
204
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
sys/dev/drm/amd/amdgpu/cz_ih.c
389
srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET,
sys/dev/drm/amd/amdgpu/cz_ih.c
63
ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 1);
sys/dev/drm/amd/amdgpu/cz_ih.c
64
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);
sys/dev/drm/amd/amdgpu/cz_ih.c
82
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0);
sys/dev/drm/amd/amdgpu/cz_ih.c
83
ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1113
tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1116
tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1117
tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1120
tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1123
tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1124
tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1208
tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1241
tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1243
tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1246
tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1248
tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1290
tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1293
tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1296
tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1299
tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1365
tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1367
tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1369
tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1381
tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1468
tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1471
tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1475
tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1478
tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1482
tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1485
tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1533
tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1577
tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1589
tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1590
tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1595
tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1596
tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1601
tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1602
tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1610
tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1611
tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1612
tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1617
tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1619
tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1624
tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1629
tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1636
tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1638
tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1643
tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1649
tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1652
tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1654
tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1660
tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1664
tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1668
tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1669
tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1670
tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1671
tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1672
tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1673
tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1701
tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1703
tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1707
tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1712
tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1834
u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1877
fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1878
fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1882
fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1883
fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1885
fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1891
fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1892
fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1894
fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1900
fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1901
fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1903
fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1908
fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1909
fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1911
fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1917
fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1918
fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1920
fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1926
fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1927
fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1929
fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1937
fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1938
fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1940
fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1948
fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1949
fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1950
fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_RED_CROSSBAR, 2);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1951
fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_BLUE_CROSSBAR, 2);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1953
fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1972
fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1973
fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1975
fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1977
fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1978
fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1979
fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1981
fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1984
fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1988
fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1997
tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2019
tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2021
tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2079
tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2081
tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2097
tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2098
tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_OVL_MODE, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2102
tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2106
tmp = REG_SET_FIELD(tmp, PRESCALE_OVL_CONTROL, OVL_PRESCALE_BYPASS, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2110
tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2111
tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, OVL_INPUT_GAMMA_MODE, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2139
tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2140
tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, OVL_DEGAMMA_MODE, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2141
tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2145
tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2146
tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, OVL_GAMUT_REMAP_MODE, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2150
tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2151
tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, OVL_REGAMMA_MODE, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2155
tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2156
tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_OVL_MODE, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2165
tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2269
cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2271
cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2282
tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2298
tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2299
tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
240
tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2959
lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2965
lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2988
lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2994
lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
3018
tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
3023
tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
308
tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
310
tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
3168
tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
3183
tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
3198
tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
342
tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
348
tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
352
tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
355
tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
sys/dev/drm/amd/amdgpu/dce_v10_0.c
387
tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
438
tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
440
tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
446
tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
448
tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
483
tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
524
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
525
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
526
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
527
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
529
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
530
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
536
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
537
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
538
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
539
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
540
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
542
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
543
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
549
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
550
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
551
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
552
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
553
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
555
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
556
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
616
tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
620
tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1139
tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1142
tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1143
tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1146
tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1149
tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1150
tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1234
tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1267
tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1269
tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1272
tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1274
tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1316
tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1319
tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1322
tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1325
tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1391
tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1393
tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1395
tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1407
tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1510
tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1513
tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1517
tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1520
tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1524
tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1527
tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1575
tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1619
tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1631
tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1632
tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1637
tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1638
tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1643
tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1644
tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1652
tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1653
tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1654
tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1659
tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1661
tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1666
tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1671
tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1678
tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1680
tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1685
tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1691
tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1694
tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1696
tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1702
tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1706
tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1710
tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1711
tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1712
tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1713
tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1714
tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1715
tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1743
tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1745
tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1749
tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1754
tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1876
u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1919
fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1920
fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1924
fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1925
fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1927
fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1933
fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1934
fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1936
fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1942
fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1943
fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1945
fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1950
fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1951
fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1953
fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1959
fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1960
fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1962
fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1968
fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1969
fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1971
fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1979
fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1980
fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1982
fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1990
fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1991
fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1992
fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_RED_CROSSBAR, 2);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1993
fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_BLUE_CROSSBAR, 2);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1995
fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2014
fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2015
fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2017
fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2019
fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2020
fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2021
fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2023
fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2026
fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2030
fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2039
tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2061
tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2063
tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2121
tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2123
tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2139
tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2143
tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2147
tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2175
tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2176
tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2177
tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, 0);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2181
tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2185
tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2189
tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2198
tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2348
cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2350
cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2361
tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2377
tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2378
tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
258
tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
3085
lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
3091
lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
3114
lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
3120
lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
3144
tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
3149
tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
326
tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
328
tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
3294
tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
3309
tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
3324
tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
360
tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
366
tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
370
tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
373
tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
sys/dev/drm/amd/amdgpu/dce_v11_0.c
404
tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
454
tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
456
tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
462
tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
464
tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
509
tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
550
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
551
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
552
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
553
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
555
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
556
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
562
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
563
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
564
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
565
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
566
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
568
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
569
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
575
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
576
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
577
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
578
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
579
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
581
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
582
tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
642
tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
646
tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
371
tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
373
tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
379
tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
381
tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
423
tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
1593
data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
1595
data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
1928
sh_mem_cfg = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
1930
sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, DEFAULT_MTYPE,
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
1932
sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, APE1_MTYPE,
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
1934
sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, PRIVATE_ATC, 0);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
1936
sh_static_mem_cfg = REG_SET_FIELD(0, SH_STATIC_MEM_CONFIG,
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
1938
sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG,
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
1940
sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG,
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
2016
tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS0, 2);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
2017
tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS1, 2);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
2018
tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS2, 2);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
2019
tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS3, 2);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3028
tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4212
value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4213
value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4214
value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4215
value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
1688
REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
1714
REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
1740
REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
1760
tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, DED_MODE, 2);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
1761
tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, PROP_FED, 1);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
1765
tmp = REG_SET_FIELD(tmp, CC_GC_EDC_CONFIG, DIS_EDC, 0) | 1;
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
1970
gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 0);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
1973
gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 1);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
1976
gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 2);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
3527
data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
3529
data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
3532
data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
3534
data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
3537
data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
3539
data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
3847
sh_static_mem_cfg = REG_SET_FIELD(0, SH_STATIC_MEM_CONFIG,
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
3849
sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG,
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
3851
sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG,
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
3860
tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_UC);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
3861
tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
3862
tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
3867
tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_NC);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
3868
tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
3869
tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
3902
tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS0, 2);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
3903
tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS1, 2);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
3904
tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS2, 2);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
3905
tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS3, 2);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
3955
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
3956
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
3957
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
3958
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4099
data = REG_SET_FIELD(0, RLC_PG_DELAY, POWER_UP_DELAY, 0x10);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4100
data = REG_SET_FIELD(data, RLC_PG_DELAY, POWER_DOWN_DELAY, 0x10);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4101
data = REG_SET_FIELD(data, RLC_PG_DELAY, CMD_PROPAGATE_DELAY, 0x10);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4102
data = REG_SET_FIELD(data, RLC_PG_DELAY, MEM_SLEEP_DELAY, 0x10);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4192
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 0);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4193
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 0);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4194
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 0);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4196
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4197
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4198
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4308
tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4310
tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4312
tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4315
tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4323
tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4349
tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4350
tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4351
tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MTYPE, 3);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4352
tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MIN_IB_AVAILSZ, 1);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4354
tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4529
tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4535
tmp = REG_SET_FIELD(RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL),
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4548
tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4558
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4560
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4563
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4565
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4566
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4567
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4568
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4586
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4589
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4591
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4593
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4608
tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4613
tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4614
tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MTYPE, 3);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4618
tmp = REG_SET_FIELD(tmp, CP_HQD_IQ_TIMER, MTYPE, 3);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4622
tmp = REG_SET_FIELD(tmp, CP_HQD_CTX_SAVE_CONTROL, MTYPE, 3);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5016
grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5018
grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5020
srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5027
grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5033
grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5035
grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5037
grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5039
srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET,
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5046
srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5049
srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5120
tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_STALL, 1);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5121
tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_CLEAR, 1);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5156
tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_STALL, 0);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5157
tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_CLEAR, 0);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
6274
tmp = REG_SET_FIELD(tmp, SPI_WCL_PIPE_PERCENT_GFX, VALUE, pipe_percent);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
6514
value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
6515
value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
6516
value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
6517
value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
1006
data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
1007
data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
1036
data = REG_SET_FIELD(0, RLC_LB_PARAMS, FIFO_SAMPLES, 0x0003);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
1037
data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLES, 0x0010);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
1038
data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLE_INTERVAL, 0x033F);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
1055
data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
1056
data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
1598
data = REG_SET_FIELD(0, WD_BUF_RESOURCE_1, INDEX_BUF_SIZE,
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
1600
data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, POS_BUF_SIZE,
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
1604
data = REG_SET_FIELD(0, WD_BUF_RESOURCE_2, CNTL_SB_BUF_SIZE,
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
1606
data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, PARAM_BUF_SIZE,
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
1612
data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE, BASE, base);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
1616
data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE_HI, BASE_HI, base);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
1620
data = REG_SET_FIELD(0, WD_POS_BUF_BASE, BASE, base);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
1624
data = REG_SET_FIELD(0, WD_POS_BUF_BASE_HI, BASE_HI, base);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
1628
data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE, BASE, base);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
1632
data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE_HI, BASE_HI, base);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
1872
data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
1874
data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
1877
data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
1879
data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
1882
data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
1884
data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
1981
tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
1986
tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
1989
tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
1991
tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2065
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2066
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2067
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2068
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2305
data = REG_SET_FIELD(data, RLC_PG_CNTL,
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2319
data = REG_SET_FIELD(data, RLC_PG_CNTL,
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2333
data = REG_SET_FIELD(data, RLC_PG_CNTL,
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2346
data = REG_SET_FIELD(data, RLC_PG_CNTL,
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2359
data = REG_SET_FIELD(data, RLC_PG_CNTL,
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2376
data = REG_SET_FIELD(data, RLC_PG_CNTL,
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2389
data = REG_SET_FIELD(data, RLC_PG_CNTL,
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2537
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2538
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2539
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2683
tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2684
tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2686
tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2713
tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2715
tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2718
tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2722
tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2772
tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2773
tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2908
tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2917
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2919
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2921
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2923
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2926
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2945
tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2955
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2957
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2960
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2962
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2963
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2964
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2965
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2983
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2986
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2988
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2990
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
3004
tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
3009
tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
3493
grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
3495
grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
3500
grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
3507
grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
4214
tmp = REG_SET_FIELD(tmp, SPI_WCL_PIPE_PERCENT_GFX, VALUE, pipe_percent);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
4517
value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
4518
value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
4519
value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
4520
value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
4577
mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
4583
mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
987
data = REG_SET_FIELD(0, RLC_LB_PARAMS, FIFO_SAMPLES, 0x0003);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
988
data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLES, 0x0010);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
989
data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLE_INTERVAL, 0x033F);
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
116
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
117
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
118
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
120
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
122
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
123
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
125
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
136
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
137
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
139
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
141
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1);
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
142
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
143
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
147
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
148
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
153
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
154
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
157
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
158
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
164
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
165
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
174
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
175
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
211
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
212
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
214
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
216
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
219
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
221
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
223
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
225
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
227
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
229
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
233
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
296
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
297
tmp = REG_SET_FIELD(tmp,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
319
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
321
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
323
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
325
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
327
tmp = REG_SET_FIELD(tmp,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
331
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
333
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
335
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
337
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
339
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
341
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
344
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c
346
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
112
tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
115
tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
116
tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
1205
srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
1211
srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
278
tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
283
tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
303
tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
520
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
522
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
524
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
526
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
528
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
530
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
551
tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
553
tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
555
tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
557
tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
559
tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
561
tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
563
tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
621
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
622
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
623
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
624
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
625
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
629
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
630
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
631
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
632
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
633
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
634
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
635
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
637
tmp = REG_SET_FIELD(0, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
638
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
643
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
644
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
645
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
655
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
656
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
657
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
685
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
686
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
687
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
742
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
743
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
744
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
748
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
862
data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
863
data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
864
data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
865
data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
867
data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
868
data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
869
data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
870
data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
885
data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
887
data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
901
data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
903
data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
98
blackout = REG_SET_FIELD(blackout,
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1340
srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1346
srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
186
blackout = REG_SET_FIELD(blackout,
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
200
tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
203
tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
204
tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
469
tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
474
tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
505
tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
745
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
747
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
749
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
751
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
753
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
755
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
757
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
778
tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
780
tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
782
tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
784
tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
786
tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
788
tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
790
tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
848
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
849
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
850
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
851
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
852
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
856
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
857
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
858
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
859
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
860
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
861
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
862
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
865
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
866
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
871
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
872
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
873
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
877
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL, 0);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
878
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED, 0);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
879
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 0);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
880
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL, 0);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
881
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED, 0);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
882
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 0);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
883
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL, 0);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
884
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED, 0);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
885
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP, 0);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
886
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL, 0);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
887
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED, 0);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
888
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP, 0);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
898
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
899
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
900
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
928
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
929
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
930
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
931
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
932
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
933
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
934
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
935
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
936
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
937
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
986
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
987
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
988
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
992
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
sys/dev/drm/amd/amdgpu/gmc_v9_0.c
301
req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
sys/dev/drm/amd/amdgpu/gmc_v9_0.c
303
req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, 0);
sys/dev/drm/amd/amdgpu/gmc_v9_0.c
304
req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
sys/dev/drm/amd/amdgpu/gmc_v9_0.c
305
req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
sys/dev/drm/amd/amdgpu/gmc_v9_0.c
306
req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
sys/dev/drm/amd/amdgpu/gmc_v9_0.c
307
req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
sys/dev/drm/amd/amdgpu/gmc_v9_0.c
308
req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
sys/dev/drm/amd/amdgpu/gmc_v9_0.c
309
req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
sys/dev/drm/amd/amdgpu/iceland_ih.c
119
interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
sys/dev/drm/amd/amdgpu/iceland_ih.c
121
interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
sys/dev/drm/amd/amdgpu/iceland_ih.c
128
ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 1);
sys/dev/drm/amd/amdgpu/iceland_ih.c
129
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
sys/dev/drm/amd/amdgpu/iceland_ih.c
130
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);
sys/dev/drm/amd/amdgpu/iceland_ih.c
133
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1);
sys/dev/drm/amd/amdgpu/iceland_ih.c
148
ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, MC_VMID, 0);
sys/dev/drm/amd/amdgpu/iceland_ih.c
151
ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, RPTR_REARM, 1);
sys/dev/drm/amd/amdgpu/iceland_ih.c
195
wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
sys/dev/drm/amd/amdgpu/iceland_ih.c
204
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
sys/dev/drm/amd/amdgpu/iceland_ih.c
389
srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET,
sys/dev/drm/amd/amdgpu/iceland_ih.c
63
ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 1);
sys/dev/drm/amd/amdgpu/iceland_ih.c
64
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);
sys/dev/drm/amd/amdgpu/iceland_ih.c
82
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0);
sys/dev/drm/amd/amdgpu/iceland_ih.c
83
ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 0);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
124
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
136
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
137
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
138
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
140
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
142
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
143
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
145
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
156
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
157
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
159
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
161
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
162
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
163
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
167
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
168
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
172
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
173
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
176
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
177
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
182
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
183
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
192
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
193
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
230
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
231
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
233
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
235
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
238
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
240
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
242
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
244
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
246
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
248
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
252
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
328
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
329
tmp = REG_SET_FIELD(tmp,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
337
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
352
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
354
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
356
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
358
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
360
tmp = REG_SET_FIELD(tmp,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
364
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
366
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
368
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
370
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
372
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
374
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
377
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/drm/amd/amdgpu/mmhub_v1_0.c
379
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
sys/dev/drm/amd/amdgpu/mxgpu_ai.c
139
reg = REG_SET_FIELD(reg, BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0,
sys/dev/drm/amd/amdgpu/mxgpu_ai.c
228
tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_MAILBOX_INT_CNTL, ACK_INT_EN,
sys/dev/drm/amd/amdgpu/mxgpu_ai.c
280
tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_MAILBOX_INT_CNTL, VALID_INT_EN,
sys/dev/drm/amd/amdgpu/mxgpu_vi.c
325
reg = REG_SET_FIELD(reg, MAILBOX_CONTROL, RCV_MSG_ACK, 1);
sys/dev/drm/amd/amdgpu/mxgpu_vi.c
347
reg = REG_SET_FIELD(reg, MAILBOX_CONTROL,
sys/dev/drm/amd/amdgpu/mxgpu_vi.c
358
reg = REG_SET_FIELD(reg, MAILBOX_MSGBUF_TRN_DW0,
sys/dev/drm/amd/amdgpu/mxgpu_vi.c
505
tmp = REG_SET_FIELD(tmp, MAILBOX_INT_CNTL, ACK_INT_EN,
sys/dev/drm/amd/amdgpu/mxgpu_vi.c
535
tmp = REG_SET_FIELD(tmp, MAILBOX_INT_CNTL, VALID_INT_EN,
sys/dev/drm/amd/amdgpu/nbio_v6_1.c
103
tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_EN, 1) |
sys/dev/drm/amd/amdgpu/nbio_v6_1.c
104
REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_MODE, 1) |
sys/dev/drm/amd/amdgpu/nbio_v6_1.c
105
REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_SIZE, 0);
sys/dev/drm/amd/amdgpu/nbio_v6_1.c
123
ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index);
sys/dev/drm/amd/amdgpu/nbio_v6_1.c
124
ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 2);
sys/dev/drm/amd/amdgpu/nbio_v6_1.c
126
ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0);
sys/dev/drm/amd/amdgpu/nbio_v6_1.c
141
interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
sys/dev/drm/amd/amdgpu/nbio_v6_1.c
143
interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
sys/dev/drm/amd/amdgpu/nbio_v6_1.c
268
data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);
sys/dev/drm/amd/amdgpu/nbio_v6_1.c
269
data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1);
sys/dev/drm/amd/amdgpu/nbio_v6_1.c
82
doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
sys/dev/drm/amd/amdgpu/nbio_v6_1.c
83
doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 2);
sys/dev/drm/amd/amdgpu/nbio_v6_1.c
85
doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);
sys/dev/drm/amd/amdgpu/nbio_v7_0.c
106
ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index);
sys/dev/drm/amd/amdgpu/nbio_v7_0.c
107
ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 2);
sys/dev/drm/amd/amdgpu/nbio_v7_0.c
109
ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0);
sys/dev/drm/amd/amdgpu/nbio_v7_0.c
216
interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
sys/dev/drm/amd/amdgpu/nbio_v7_0.c
218
interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
sys/dev/drm/amd/amdgpu/nbio_v7_0.c
80
doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
sys/dev/drm/amd/amdgpu/nbio_v7_0.c
81
doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 2);
sys/dev/drm/amd/amdgpu/nbio_v7_0.c
83
doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);
sys/dev/drm/amd/amdgpu/nbio_v7_4.c
100
REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_SIZE, 0);
sys/dev/drm/amd/amdgpu/nbio_v7_4.c
117
ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index);
sys/dev/drm/amd/amdgpu/nbio_v7_4.c
118
ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 2);
sys/dev/drm/amd/amdgpu/nbio_v7_4.c
120
ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0);
sys/dev/drm/amd/amdgpu/nbio_v7_4.c
178
interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
sys/dev/drm/amd/amdgpu/nbio_v7_4.c
180
interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
sys/dev/drm/amd/amdgpu/nbio_v7_4.c
78
doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
sys/dev/drm/amd/amdgpu/nbio_v7_4.c
79
doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 2);
sys/dev/drm/amd/amdgpu/nbio_v7_4.c
81
doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);
sys/dev/drm/amd/amdgpu/nbio_v7_4.c
98
tmp = REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_EN, 1) |
sys/dev/drm/amd/amdgpu/nbio_v7_4.c
99
REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_MODE, 1) |
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
1030
sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
1035
sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
1046
sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
1051
sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
277
ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
279
ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
346
rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
349
ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
389
f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
391
f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
434
rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
436
rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
437
rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
454
rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
463
rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
467
ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
469
ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
986
tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
993
tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
1365
sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
1370
sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
1381
sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
1386
sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
451
ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
453
ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
520
rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
523
ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
582
f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
584
f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
593
f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
595
f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
624
f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
626
f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
672
rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
674
rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
675
rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
693
rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
701
doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL,
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
703
doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
705
doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
720
wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
724
wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
731
rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
735
ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
737
ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
1462
sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
573
rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
576
ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
635
f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
670
f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
704
rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
706
rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
707
rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
724
rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
743
doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
744
doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
747
doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
762
temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
768
temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
780
wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 1);
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
782
wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 0);
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
786
rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
790
ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
792
ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
sys/dev/drm/amd/amdgpu/soc15.c
223
grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
sys/dev/drm/amd/amdgpu/soc15.c
224
grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
sys/dev/drm/amd/amdgpu/soc15.c
225
grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
sys/dev/drm/amd/amdgpu/soc15.c
226
grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
sys/dev/drm/amd/amdgpu/tonga_ih.c
115
interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
sys/dev/drm/amd/amdgpu/tonga_ih.c
117
interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
sys/dev/drm/amd/amdgpu/tonga_ih.c
127
ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
sys/dev/drm/amd/amdgpu/tonga_ih.c
128
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);
sys/dev/drm/amd/amdgpu/tonga_ih.c
130
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1);
sys/dev/drm/amd/amdgpu/tonga_ih.c
131
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);
sys/dev/drm/amd/amdgpu/tonga_ih.c
134
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 1);
sys/dev/drm/amd/amdgpu/tonga_ih.c
152
ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR,
sys/dev/drm/amd/amdgpu/tonga_ih.c
154
ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR,
sys/dev/drm/amd/amdgpu/tonga_ih.c
157
ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR,
sys/dev/drm/amd/amdgpu/tonga_ih.c
206
wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
sys/dev/drm/amd/amdgpu/tonga_ih.c
215
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
sys/dev/drm/amd/amdgpu/tonga_ih.c
412
srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET,
sys/dev/drm/amd/amdgpu/tonga_ih.c
62
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);
sys/dev/drm/amd/amdgpu/tonga_ih.c
63
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1);
sys/dev/drm/amd/amdgpu/tonga_ih.c
79
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0);
sys/dev/drm/amd/amdgpu/tonga_ih.c
80
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0);
sys/dev/drm/amd/amdgpu/uvd_v5_0.c
396
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
sys/dev/drm/amd/amdgpu/uvd_v5_0.c
397
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
sys/dev/drm/amd/amdgpu/uvd_v5_0.c
398
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
sys/dev/drm/amd/amdgpu/uvd_v5_0.c
399
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
sys/dev/drm/amd/amdgpu/uvd_v5_0.c
400
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
sys/dev/drm/amd/amdgpu/uvd_v5_0.c
401
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
1150
srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_UVD, 1);
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
820
tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
821
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
822
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
823
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
824
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
825
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
1067
tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
1068
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
1069
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
1070
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
1071
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
1072
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
1470
srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
900
tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, size);
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
901
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
sys/dev/drm/amd/amdgpu/vce_v3_0.c
631
srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE0, 1);
sys/dev/drm/amd/amdgpu/vce_v3_0.c
632
srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE1, 1);
sys/dev/drm/amd/amdgpu/vce_v3_0.c
636
srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE0, 1);
sys/dev/drm/amd/amdgpu/vce_v3_0.c
637
srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE1, 1);
sys/dev/drm/amd/amdgpu/vce_v4_0.c
716
srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE0, 1);
sys/dev/drm/amd/amdgpu/vce_v4_0.c
717
srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE1, 1);
sys/dev/drm/amd/amdgpu/vce_v4_0.c
721
srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE0, 1);
sys/dev/drm/amd/amdgpu/vce_v4_0.c
722
srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE1, 1);
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
1066
tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
1067
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
1068
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
1069
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
1070
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
893
tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
894
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
895
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
896
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
897
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
sys/dev/drm/amd/amdgpu/vega10_ih.c
105
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SPACE, 1);
sys/dev/drm/amd/amdgpu/vega10_ih.c
109
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SPACE, 4);
sys/dev/drm/amd/amdgpu/vega10_ih.c
112
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
sys/dev/drm/amd/amdgpu/vega10_ih.c
113
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 1);
sys/dev/drm/amd/amdgpu/vega10_ih.c
114
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);
sys/dev/drm/amd/amdgpu/vega10_ih.c
116
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1);
sys/dev/drm/amd/amdgpu/vega10_ih.c
117
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1);
sys/dev/drm/amd/amdgpu/vega10_ih.c
118
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0);
sys/dev/drm/amd/amdgpu/vega10_ih.c
119
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);
sys/dev/drm/amd/amdgpu/vega10_ih.c
122
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 1);
sys/dev/drm/amd/amdgpu/vega10_ih.c
140
ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR,
sys/dev/drm/amd/amdgpu/vega10_ih.c
142
ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR,
sys/dev/drm/amd/amdgpu/vega10_ih.c
145
ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR,
sys/dev/drm/amd/amdgpu/vega10_ih.c
153
tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL,
sys/dev/drm/amd/amdgpu/vega10_ih.c
158
tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1);
sys/dev/drm/amd/amdgpu/vega10_ih.c
204
wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
sys/dev/drm/amd/amdgpu/vega10_ih.c
216
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
sys/dev/drm/amd/amdgpu/vega10_ih.c
49
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);
sys/dev/drm/amd/amdgpu/vega10_ih.c
50
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1);
sys/dev/drm/amd/amdgpu/vega10_ih.c
66
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0);
sys/dev/drm/amd/amdgpu/vega10_ih.c
67
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0);
sys/dev/drm/amd/amdgpu/vi.c
362
srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, PIPEID, pipe);
sys/dev/drm/amd/amdgpu/vi.c
363
srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, MEID, me);
sys/dev/drm/amd/amdgpu/vi.c
364
srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, vmid);
sys/dev/drm/amd/amdgpu/vi.c
365
srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, QUEUEID, queue);
sys/dev/drm/amd/amdgpu/vi.c
883
tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 1);
sys/dev/drm/amd/amdgpu/vi.c
885
tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 0);
sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c
896
data = REG_SET_FIELD(data, DIDT_SQ_EDC_CTRL, EDC_EN, en);
sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c
897
data = REG_SET_FIELD(data, DIDT_SQ_EDC_CTRL, EDC_SW_RST, ~en);
sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c
903
data = REG_SET_FIELD(data, DIDT_DB_EDC_CTRL, EDC_EN, en);
sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c
904
data = REG_SET_FIELD(data, DIDT_DB_EDC_CTRL, EDC_SW_RST, ~en);
sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c
910
data = REG_SET_FIELD(data, DIDT_TD_EDC_CTRL, EDC_EN, en);
sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c
911
data = REG_SET_FIELD(data, DIDT_TD_EDC_CTRL, EDC_SW_RST, ~en);
sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c
917
data = REG_SET_FIELD(data, DIDT_TCP_EDC_CTRL, EDC_EN, en);
sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c
918
data = REG_SET_FIELD(data, DIDT_TCP_EDC_CTRL, EDC_SW_RST, ~en);
sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c
924
data = REG_SET_FIELD(data, DIDT_DBR_EDC_CTRL, EDC_EN, en);
sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c
925
data = REG_SET_FIELD(data, DIDT_DBR_EDC_CTRL, EDC_SW_RST, ~en);
sys/dev/drm/amd/powerplay/hwmgr/vega10_thermal.c
143
REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
sys/dev/drm/amd/powerplay/hwmgr/vega10_thermal.c
146
REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
sys/dev/drm/amd/powerplay/hwmgr/vega10_thermal.c
163
REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
sys/dev/drm/amd/powerplay/hwmgr/vega10_thermal.c
167
REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
sys/dev/drm/amd/powerplay/hwmgr/vega10_thermal.c
279
REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),
sys/dev/drm/amd/powerplay/hwmgr/vega10_thermal.c
327
REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
sys/dev/drm/amd/powerplay/hwmgr/vega10_thermal.c
384
val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
sys/dev/drm/amd/powerplay/hwmgr/vega10_thermal.c
385
val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
sys/dev/drm/amd/powerplay/hwmgr/vega10_thermal.c
386
val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
sys/dev/drm/amd/powerplay/hwmgr/vega10_thermal.c
387
val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
sys/dev/drm/amd/powerplay/hwmgr/vega10_thermal.c
408
REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
sys/dev/drm/amd/powerplay/hwmgr/vega10_thermal.c
414
REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
sys/dev/drm/amd/powerplay/hwmgr/vega12_thermal.c
190
val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
sys/dev/drm/amd/powerplay/hwmgr/vega12_thermal.c
191
val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
sys/dev/drm/amd/powerplay/hwmgr/vega12_thermal.c
192
val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
sys/dev/drm/amd/powerplay/hwmgr/vega12_thermal.c
193
val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
sys/dev/drm/amd/powerplay/hwmgr/vega20_thermal.c
161
REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),
sys/dev/drm/amd/powerplay/hwmgr/vega20_thermal.c
204
REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
sys/dev/drm/amd/powerplay/hwmgr/vega20_thermal.c
95
REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
sys/dev/drm/amd/powerplay/hwmgr/vega20_thermal.c
98
REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
