sys/dev/drm/amd/display/dc/dce/dce_i2c_hw.c

214

value = REG_SET_4(DC_I2C_DATA, 0,

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

108

REG_SET_4(AFMT_GENERIC_HDR, 0,

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

487

REG_SET_4(DP_MSA_TIMING_PARAM3, 0,

sys/dev/drm/amd/display/dc/dce/dce_transform.c

1230

REG_SET_4(REGAMMA_CNTLA_REGION_0_1, 0,

sys/dev/drm/amd/display/dc/dce/dce_transform.c

1237

REG_SET_4(REGAMMA_CNTLA_REGION_2_3, 0,

sys/dev/drm/amd/display/dc/dce/dce_transform.c

1244

REG_SET_4(REGAMMA_CNTLA_REGION_4_5, 0,

sys/dev/drm/amd/display/dc/dce/dce_transform.c

1251

REG_SET_4(REGAMMA_CNTLA_REGION_6_7, 0,

sys/dev/drm/amd/display/dc/dce/dce_transform.c

1258

REG_SET_4(REGAMMA_CNTLA_REGION_8_9, 0,

sys/dev/drm/amd/display/dc/dce/dce_transform.c

1265

REG_SET_4(REGAMMA_CNTLA_REGION_10_11, 0,

sys/dev/drm/amd/display/dc/dce/dce_transform.c

1272

REG_SET_4(REGAMMA_CNTLA_REGION_12_13, 0,

sys/dev/drm/amd/display/dc/dce/dce_transform.c

1279

REG_SET_4(REGAMMA_CNTLA_REGION_14_15, 0,

sys/dev/drm/amd/display/dc/dce/dce_transform.c

222

REG_SET_4(SCL_COEF_RAM_TAP_DATA, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_cm_common.c

115

REG_SET_4(reg_region_cur, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c

278

REG_SET_4(SCL_COEF_RAM_TAP_DATA, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c

554

REG_SET_4(SCL_TAP_CONTROL, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c

709

REG_SET_4(SCL_TAP_CONTROL, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

520

REG_SET_4(DCN_EXPANSION_MODE, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

1093

REG_SET_4(OTG_TEST_PATTERN_CONTROL, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

730

REG_SET_4(OTG_TRIGA_CNTL, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

444

REG_SET_4(DP_MSA_TIMING_PARAM3, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

96

REG_SET_4(AFMT_GENERIC_HDR, 0,

sys/dev/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c

310

value = REG_SET_4(DC_I2C_DATA, 0,