sys/dev/drm/amd/display/dc/dce/dce_abm.c

262

REG_SET_3(DC_ABM1_HG_MISC_CTRL, 0,

sys/dev/drm/amd/display/dc/dce/dce_abm.c

267

REG_SET_3(DC_ABM1_IPCSC_COEFF_SEL, 0,

sys/dev/drm/amd/display/dc/dce/dce_abm.c

285

REG_SET_3(DC_ABM1_HGLS_REG_READ_PROGRESS, 0,

sys/dev/drm/amd/display/dc/dce/dce_i2c_hw.c

132

REG_SET_3(DC_I2C_DATA, 0,

sys/dev/drm/amd/display/dc/dce/dce_ipp.c

102

REG_SET_3(CUR_COLOR1, 0,

sys/dev/drm/amd/display/dc/dce/dce_ipp.c

107

REG_SET_3(CUR_COLOR2, 0,

sys/dev/drm/amd/display/dc/dce/dce_ipp.c

187

REG_SET_3(DC_LUT_CONTROL, 0,

sys/dev/drm/amd/display/dc/dce/dce_ipp.c

226

REG_SET_3(DEGAMMA_CONTROL, 0,

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c

171

REG_SET_3(DP_DPHY_SYM0, 0,

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c

179

REG_SET_3(DP_DPHY_SYM1, 0,

sys/dev/drm/amd/display/dc/dce/dce_transform.c

210

REG_SET_3(SCL_COEF_RAM_SELECT, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c

326

REG_SET_3(FORMAT_CONTROL, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c

332

REG_SET_3(FORMAT_CONTROL, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

737

REG_SET_3(FORMAT_CONTROL, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c

265

REG_SET_3(SCL_COEF_RAM_TAP_SELECT, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c

538

REG_SET_3(DSCL_AUTOCAL, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c

666

REG_SET_3(DSCL_AUTOCAL, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

652

REG_SET_3(DCN_SURF0_TTU_CNTL0, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

661

REG_SET_3(DCN_SURF1_TTU_CNTL0, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

670

REG_SET_3(DCN_CUR0_TTU_CNTL0, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.c

141

REG_SET_3(DP_DPHY_SYM0, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.c

149

REG_SET_3(DP_DPHY_SYM1, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

510

REG_SET_3(OTG_BLACK_COLOR, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

685

REG_SET_3(OTG_TRIGA_CNTL, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

694

REG_SET_3(OTG_TRIGA_CNTL, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

90

REG_SET_3(OTG_3D_STRUCTURE_CONTROL, 0,

sys/dev/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c

394

REG_SET_3(DC_I2C_DATA, 0,