sys/dev/drm/amd/display/dc/dce/dce_aux.c

216

value = REG_SET_2(AUX_SW_DATA, value,

sys/dev/drm/amd/display/dc/dce/dce_hwseq.c

71

REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val,

sys/dev/drm/amd/display/dc/dce/dce_hwseq.c

76

REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val,

sys/dev/drm/amd/display/dc/dce/dce_i2c_hw.c

221

value = REG_SET_2(DC_I2C_DATA, 0,

sys/dev/drm/amd/display/dc/dce/dce_i2c_hw.c

229

REG_SET_2(DC_I2C_DATA, value,

sys/dev/drm/amd/display/dc/dce/dce_ipp.c

117

REG_SET_2(CUR_SIZE, 0,

sys/dev/drm/amd/display/dc/dce/dce_ipp.c

147

REG_SET_2(PRESCALE_VALUES_GRPH_R, 0,

sys/dev/drm/amd/display/dc/dce/dce_ipp.c

151

REG_SET_2(PRESCALE_VALUES_GRPH_G, 0,

sys/dev/drm/amd/display/dc/dce/dce_ipp.c

155

REG_SET_2(PRESCALE_VALUES_GRPH_B, 0,

sys/dev/drm/amd/display/dc/dce/dce_ipp.c

55

REG_SET_2(CUR_POSITION, 0,

sys/dev/drm/amd/display/dc/dce/dce_ipp.c

59

REG_SET_2(CUR_HOT_SPOT, 0,

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c

187

REG_SET_2(DP_DPHY_SYM2, 0,

sys/dev/drm/amd/display/dc/dce/dce_mem_input.c

172

REG_SET_2(DPG_PIPE_URGENCY_CONTROL, 0,

sys/dev/drm/amd/display/dc/dce/dce_mem_input.c

186

REG_SET_2(DPG_PIPE_URGENCY_CONTROL, 0,

sys/dev/drm/amd/display/dc/dce/dce_mem_input.c

190

REG_SET_2(DPG_PIPE_URGENT_LEVEL_CONTROL, 0,

sys/dev/drm/amd/display/dc/dce/dce_mem_input.c

451

REG_SET_2(GRPH_SWAP_CNTL, 0,

sys/dev/drm/amd/display/dc/dce/dce_mem_input.c

657

REG_SET_2(GRPH_SECONDARY_SURFACE_ADDRESS, 0,

sys/dev/drm/amd/display/dc/dce/dce_opp.c

328

REG_SET_2(FMT_CLAMP_CNTL, 0,

sys/dev/drm/amd/display/dc/dce/dce_opp.c

336

REG_SET_2(FMT_CLAMP_CNTL, 0,

sys/dev/drm/amd/display/dc/dce/dce_opp.c

341

REG_SET_2(FMT_CLAMP_CNTL, 0,

sys/dev/drm/amd/display/dc/dce/dce_opp.c

346

REG_SET_2(FMT_CLAMP_CNTL, 0,

sys/dev/drm/amd/display/dc/dce/dce_opp.c

352

REG_SET_2(FMT_CLAMP_CNTL, 0,

sys/dev/drm/amd/display/dc/dce/dce_opp.c

357

REG_SET_2(FMT_CLAMP_COMPONENT_R, 0,

sys/dev/drm/amd/display/dc/dce/dce_opp.c

361

REG_SET_2(FMT_CLAMP_COMPONENT_G, 0,

sys/dev/drm/amd/display/dc/dce/dce_opp.c

365

REG_SET_2(FMT_CLAMP_COMPONENT_B, 0,

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

455

REG_SET_2(DP_MSA_TIMING_PARAM1, 0,

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

482

REG_SET_2(DP_MSA_TIMING_PARAM2, 0,

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

499

REG_SET_2(DP_MSA_TIMING_PARAM4, 0,

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

714

REG_SET_2(DP_MSE_RATE_CNTL, 0,

sys/dev/drm/amd/display/dc/dce/dce_transform.c

1214

REG_SET_2(REGAMMA_CNTLA_START_CNTL, 0,

sys/dev/drm/amd/display/dc/dce/dce_transform.c

1224

REG_SET_2(REGAMMA_CNTLA_END_CNTL2, 0,

sys/dev/drm/amd/display/dc/dce/dce_transform.c

131

REG_SET_2(SCL_TAP_CONTROL, 0,

sys/dev/drm/amd/display/dc/dce/dce_transform.c

172

REG_SET_2(EXT_OVERSCAN_LEFT_RIGHT, 0,

sys/dev/drm/amd/display/dc/dce/dce_transform.c

175

REG_SET_2(EXT_OVERSCAN_TOP_BOTTOM, 0,

sys/dev/drm/amd/display/dc/dce/dce_transform.c

239

REG_SET_2(VIEWPORT_START, 0,

sys/dev/drm/amd/display/dc/dce/dce_transform.c

243

REG_SET_2(VIEWPORT_SIZE, 0,

sys/dev/drm/amd/display/dc/dce/dce_transform.c

293

REG_SET_2(SCL_HORZ_FILTER_INIT, 0,

sys/dev/drm/amd/display/dc/dce/dce_transform.c

297

REG_SET_2(SCL_VERT_FILTER_INIT, 0,

sys/dev/drm/amd/display/dc/dce/dce_transform.c

331

REG_SET_2(LB_MEMORY_CTRL, 0,

sys/dev/drm/amd/display/dc/dce/dce_transform.c

443

REG_SET_2(OUT_CLAMP_CONTROL_B_CB, 0,

sys/dev/drm/amd/display/dc/dce/dce_transform.c

447

REG_SET_2(OUT_CLAMP_CONTROL_G_Y, 0,

sys/dev/drm/amd/display/dc/dce/dce_transform.c

451

REG_SET_2(OUT_CLAMP_CONTROL_R_CR, 0,

sys/dev/drm/amd/display/dc/dce/dce_transform.c

805

REG_SET_2(GAMUT_REMAP_C11_C12, 0,

sys/dev/drm/amd/display/dc/dce/dce_transform.c

808

REG_SET_2(GAMUT_REMAP_C13_C14, 0,

sys/dev/drm/amd/display/dc/dce/dce_transform.c

811

REG_SET_2(GAMUT_REMAP_C21_C22, 0,

sys/dev/drm/amd/display/dc/dce/dce_transform.c

814

REG_SET_2(GAMUT_REMAP_C23_C24, 0,

sys/dev/drm/amd/display/dc/dce/dce_transform.c

817

REG_SET_2(GAMUT_REMAP_C31_C32, 0,

sys/dev/drm/amd/display/dc/dce/dce_transform.c

820

REG_SET_2(GAMUT_REMAP_C33_C34, 0,

sys/dev/drm/amd/display/dc/dce/dce_transform.c

967

REG_SET_2(OUTPUT_CSC_C11_C12, 0,

sys/dev/drm/amd/display/dc/dce/dce_transform.c

972

REG_SET_2(OUTPUT_CSC_C13_C14, 0,

sys/dev/drm/amd/display/dc/dce/dce_transform.c

977

REG_SET_2(OUTPUT_CSC_C21_C22, 0,

sys/dev/drm/amd/display/dc/dce/dce_transform.c

982

REG_SET_2(OUTPUT_CSC_C23_C24, 0,

sys/dev/drm/amd/display/dc/dce/dce_transform.c

987

REG_SET_2(OUTPUT_CSC_C31_C32, 0,

sys/dev/drm/amd/display/dc/dce/dce_transform.c

992

REG_SET_2(OUTPUT_CSC_C33_C34, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_cm_common.c

104

REG_SET_2(reg->start_end_cntl2_r, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_cm_common.c

56

REG_SET_2(cur_csc_reg, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_cm_common.c

73

REG_SET_2(reg->start_cntl_b, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_cm_common.c

76

REG_SET_2(reg->start_cntl_g, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_cm_common.c

79

REG_SET_2(reg->start_cntl_r, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_cm_common.c

92

REG_SET_2(reg->start_end_cntl2_b, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_cm_common.c

98

REG_SET_2(reg->start_end_cntl2_g, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

531

REG_SET_2(CM_BNS_VALUES_R, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

535

REG_SET_2(CM_BNS_VALUES_G, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

539

REG_SET_2(CM_BNS_VALUES_B, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c

108

REG_SET_2(DSCL_EXT_OVERSCAN_LEFT_RIGHT, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c

112

REG_SET_2(DSCL_EXT_OVERSCAN_TOP_BOTTOM, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c

125

REG_SET_2(OTG_H_BLANK, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c

129

REG_SET_2(OTG_V_BLANK, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c

224

REG_SET_2(LB_MEMORY_CTRL, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c

382

REG_SET_2(SCL_MODE, scl_mode,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c

545

REG_SET_2(SCL_BLACK_OFFSET, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c

550

REG_SET_2(SCL_BLACK_OFFSET, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c

588

REG_SET_2(SCL_HORZ_FILTER_INIT, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c

594

REG_SET_2(SCL_HORZ_FILTER_INIT_C, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c

600

REG_SET_2(SCL_VERT_FILTER_INIT, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c

606

REG_SET_2(SCL_VERT_FILTER_INIT_BOT, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c

612

REG_SET_2(SCL_VERT_FILTER_INIT_C, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c

618

REG_SET_2(SCL_VERT_FILTER_INIT_BOT_C, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c

632

REG_SET_2(RECOUT_START, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c

638

REG_SET_2(RECOUT_SIZE, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c

675

REG_SET_2(MPC_SIZE, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c

696

REG_SET_2(SCL_BLACK_OFFSET, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c

701

REG_SET_2(SCL_BLACK_OFFSET, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

1076

REG_SET_2(CURSOR_SETTINS, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

1146

REG_SET_2(CURSOR_POSITION, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

1150

REG_SET_2(CURSOR_HOT_SPOT, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

554

REG_SET_2(BLANK_OFFSET_0, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

564

REG_SET_2(DST_AFTER_SCALER, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

569

REG_SET_2(PREFETCH_SETTINS, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

573

REG_SET_2(PREFETCH_SETTINGS, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

577

REG_SET_2(VBLANK_PARAMETERS_0, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

605

REG_SET_2(PER_LINE_DELIVERY_PRE, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

609

REG_SET_2(PER_LINE_DELIVERY, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

641

REG_SET_2(DCN_TTU_QOS_WM, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

645

REG_SET_2(DCN_GLOBAL_TTU_CNTL, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

732

REG_SET_2(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

772

REG_SET_2(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

779

REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

791

REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

795

REG_SET_2(DCSURF_PRI_VIEWPORT_START, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

800

REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

804

REG_SET_2(DCSURF_SEC_VIEWPORT_START, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

809

REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION_C, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

813

REG_SET_2(DCSURF_PRI_VIEWPORT_START_C, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.c

157

REG_SET_2(DP_DPHY_SYM2, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

1000

REG_SET_2(OTG_TEST_PATTERN_COLOR, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

1012

REG_SET_2(OTG_TEST_PATTERN_COLOR, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

162

REG_SET_2(OTG_VERTICAL_INTERRUPT0_POSITION, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

75

REG_SET_2(OTG_VUPDATE_PARAM, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

802

REG_SET_2(OTG_STATIC_SCREEN_CONTROL, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

416

REG_SET_2(DP_MSA_TIMING_PARAM1, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

440

REG_SET_2(DP_MSA_TIMING_PARAM2, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

455

REG_SET_2(DP_MSA_TIMING_PARAM4, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

623

REG_SET_2(DP_MSE_RATE_CNTL, 0,

sys/dev/drm/amd/display/dc/gpio/hw_ddc.c

95

REG_SET_2(gpio.MASK_reg, regval,

sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c

246

value = REG_SET_2(AUX_SW_DATA, value,

sys/dev/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c

317

value = REG_SET_2(DC_I2C_DATA, 0,

sys/dev/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c

325

REG_SET_2(DC_I2C_DATA, value,