sys/dev/drm/amd/amdgpu/cikd.h

223

#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))

sys/dev/drm/amd/amdgpu/soc15d.h

48

#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))

sys/dev/drm/amd/amdgpu/vid.h

105

#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))

sys/dev/drm/amd/display/dc/dce/dce_audio.c

62

REG_SET(AZALIA_F0_CODEC_ENDPOINT_INDEX, 0,

sys/dev/drm/amd/display/dc/dce/dce_audio.c

66

REG_SET(AZALIA_F0_CODEC_ENDPOINT_DATA, 0,

sys/dev/drm/amd/display/dc/dce/dce_audio.c

80

REG_SET(AZALIA_F0_CODEC_ENDPOINT_INDEX, 0,

sys/dev/drm/amd/display/dc/dce/dce_aux.c

220

value = REG_SET(AUX_SW_DATA, value,

sys/dev/drm/amd/display/dc/dce/dce_aux.c

224

value = REG_SET(AUX_SW_DATA, value,

sys/dev/drm/amd/display/dc/dce/dce_aux.c

237

value = REG_SET(AUX_SW_DATA, value,

sys/dev/drm/amd/display/dc/dce/dce_ipp.c

127

REG_SET(CUR_SURFACE_ADDRESS_HIGH, 0,

sys/dev/drm/amd/display/dc/dce/dce_ipp.c

130

REG_SET(CUR_SURFACE_ADDRESS, 0,

sys/dev/drm/amd/display/dc/dce/dce_ipp.c

178

REG_SET(DCFE_MEM_PWR_CTRL, 0, DCP_LUT_MEM_PWR_DIS, 1);

sys/dev/drm/amd/display/dc/dce/dce_ipp.c

181

REG_SET(DC_LUT_WRITE_EN_MASK, 0, DC_LUT_WRITE_EN_MASK, 0x7);

sys/dev/drm/amd/display/dc/dce/dce_ipp.c

193

REG_SET(DC_LUT_RW_INDEX, 0,

sys/dev/drm/amd/display/dc/dce/dce_ipp.c

197

REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR,

sys/dev/drm/amd/display/dc/dce/dce_ipp.c

200

REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR,

sys/dev/drm/amd/display/dc/dce/dce_ipp.c

203

REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR,

sys/dev/drm/amd/display/dc/dce/dce_ipp.c

210

REG_SET(DCFE_MEM_PWR_CTRL, 0, DCP_LUT_MEM_PWR_DIS, 0);

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c

482

REG_SET(DP_CONFIG, 0,

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c

557

REG_SET(DP_DPHY_TRAINING_PATTERN_SEL, 0,

sys/dev/drm/amd/display/dc/dce/dce_mem_input.c

413

REG_SET(GRPH_X_START, 0,

sys/dev/drm/amd/display/dc/dce/dce_mem_input.c

416

REG_SET(GRPH_Y_START, 0,

sys/dev/drm/amd/display/dc/dce/dce_mem_input.c

419

REG_SET(GRPH_X_END, 0,

sys/dev/drm/amd/display/dc/dce/dce_mem_input.c

422

REG_SET(GRPH_Y_END, 0,

sys/dev/drm/amd/display/dc/dce/dce_mem_input.c

425

REG_SET(GRPH_PITCH, 0,

sys/dev/drm/amd/display/dc/dce/dce_mem_input.c

428

REG_SET(HW_ROTATION, 0,

sys/dev/drm/amd/display/dc/dce/dce_mem_input.c

594

REG_SET(DMIF_BUFFER_CONTROL, dmif_buffer_control,

sys/dev/drm/amd/display/dc/dce/dce_mem_input.c

631

REG_SET(DMIF_BUFFER_CONTROL, dmif_buffer_control,

sys/dev/drm/amd/display/dc/dce/dce_mem_input.c

653

REG_SET(GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 0,

sys/dev/drm/amd/display/dc/dce/dce_mem_input.c

667

REG_SET(GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 0,

sys/dev/drm/amd/display/dc/dce/dce_mem_input.c

671

REG_SET(GRPH_PRIMARY_SURFACE_ADDRESS, 0,

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

1335

REG_SET(AFMT_AUDIO_SRC_CONTROL, 0, AFMT_AUDIO_SRC_SELECT, az_inst);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

1435

REG_SET(DP_SEC_AUD_N, 0,

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

1439

REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE,

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

446

REG_SET(DP_MSA_COLORIMETRY, 0, DP_MSA_MISC0, misc0);

sys/dev/drm/amd/display/dc/dce/dce_transform.c

1004

REG_SET(OUTPUT_CSC_CONTROL, 0,

sys/dev/drm/amd/display/dc/dce/dce_transform.c

1009

REG_SET(OUTPUT_CSC_CONTROL, 0,

sys/dev/drm/amd/display/dc/dce/dce_transform.c

1016

REG_SET(OUTPUT_CSC_CONTROL, 0,

sys/dev/drm/amd/display/dc/dce/dce_transform.c

1021

REG_SET(OUTPUT_CSC_CONTROL, 0,

sys/dev/drm/amd/display/dc/dce/dce_transform.c

1027

REG_SET(OUTPUT_CSC_CONTROL, 0,

sys/dev/drm/amd/display/dc/dce/dce_transform.c

1033

REG_SET(OUTPUT_CSC_CONTROL, 0,

sys/dev/drm/amd/display/dc/dce/dce_transform.c

1044

REG_SET(OUTPUT_CSC_CONTROL, 0,

sys/dev/drm/amd/display/dc/dce/dce_transform.c

1050

REG_SET(OUTPUT_CSC_CONTROL, 0,

sys/dev/drm/amd/display/dc/dce/dce_transform.c

1056

REG_SET(OUTPUT_CSC_CONTROL, 0,

sys/dev/drm/amd/display/dc/dce/dce_transform.c

1062

REG_SET(OUTPUT_CSC_CONTROL, 0,

sys/dev/drm/amd/display/dc/dce/dce_transform.c

1071

REG_SET(OUTPUT_CSC_CONTROL, 0,

sys/dev/drm/amd/display/dc/dce/dce_transform.c

120

REG_SET(SCL_BYPASS_CONTROL, 0, SCL_BYPASS_MODE, 0);

sys/dev/drm/amd/display/dc/dce/dce_transform.c

1218

REG_SET(REGAMMA_CNTLA_SLOPE_CNTL, 0,

sys/dev/drm/amd/display/dc/dce/dce_transform.c

1221

REG_SET(REGAMMA_CNTLA_END_CNTL1, 0,

sys/dev/drm/amd/display/dc/dce/dce_transform.c

1321

REG_SET(REGAMMA_CONTROL, 0,

sys/dev/drm/amd/display/dc/dce/dce_transform.c

144

REG_SET(SCL_CONTROL, 0, SCL_BOUNDARY_MODE, 1);

sys/dev/drm/amd/display/dc/dce/dce_transform.c

199

REG_SET(DCFE_MEM_PWR_CTRL, power_ctl, SCL_COEFF_MEM_PWR_DIS, 1);

sys/dev/drm/amd/display/dc/dce/dce_transform.c

287

REG_SET(SCL_HORZ_FILTER_SCALE_RATIO, 0,

sys/dev/drm/amd/display/dc/dce/dce_transform.c

290

REG_SET(SCL_VERT_FILTER_SCALE_RATIO, 0,

sys/dev/drm/amd/display/dc/dce/dce_transform.c

358

REG_SET(SCL_VERT_FILTER_CONTROL, 0,

sys/dev/drm/amd/display/dc/dce/dce_transform.c

373

REG_SET(SCL_HORZ_FILTER_CONTROL, 0,

sys/dev/drm/amd/display/dc/dce/dce_transform.c

538

REG_SET(OUT_ROUND_CONTROL, 0, OUT_ROUND_TRUNC_MODE, depth_bits);

sys/dev/drm/amd/display/dc/dce/dce_transform.c

744

REG_SET(DENORM_CONTROL, 0, DENORM_MODE, denorm_mode);

sys/dev/drm/amd/display/dc/dce/dce_transform.c

824

REG_SET(GAMUT_REMAP_CONTROL, 0, GRPH_GAMUT_REMAP_MODE, 1);

sys/dev/drm/amd/display/dc/dce/dce_transform.c

826

REG_SET(GAMUT_REMAP_CONTROL, 0, GRPH_GAMUT_REMAP_MODE, 0);

sys/dev/drm/amd/display/dc/dcn10/dcn10_cm_common.c

102

REG_SET(reg->start_end_cntl1_r, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_cm_common.c

83

REG_SET(reg->start_slope_cntl_b, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_cm_common.c

85

REG_SET(reg->start_slope_cntl_g, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_cm_common.c

87

REG_SET(reg->start_slope_cntl_r, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_cm_common.c

90

REG_SET(reg->start_end_cntl1_b, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_cm_common.c

96

REG_SET(reg->start_end_cntl1_g, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c

133

REG_SET(CM_GAMUT_REMAP_CONTROL, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c

266

REG_SET(CM_RGAM_CONTROL, 0, CM_RGAM_LUT_MODE, re_mode);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c

397

REG_SET(CNVC_SURFACE_PIXEL_FORMAT, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

131

REG_SET(CM_GAMUT_REMAP_CONTROL, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

185

REG_SET(

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

232

REG_SET(CM_TEST_DEBUG_INDEX, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

266

REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

354

REG_SET(CM_MEM_PWR_CTRL, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

367

REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].red_reg);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

368

REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].green_reg);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

369

REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].blue_reg);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

371

REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].delta_red_reg);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

372

REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].delta_green_reg);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

373

REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].delta_blue_reg);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

389

REG_SET(CM_RGAM_LUT_INDEX, 0, CM_RGAM_LUT_INDEX, 0);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

464

REG_SET(CM_ICSC_CONTROL, 0, CM_ICSC_MODE, 0);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

487

REG_SET(CM_TEST_DEBUG_INDEX, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

520

REG_SET(CM_ICSC_CONTROL, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

608

REG_SET(CM_MEM_PWR_CTRL, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

695

REG_SET(CM_DGAM_LUT_INDEX, 0, CM_DGAM_LUT_INDEX, 0);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

697

REG_SET(CM_DGAM_LUT_DATA, 0, CM_DGAM_LUT_DATA, rgb[i].red_reg);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

698

REG_SET(CM_DGAM_LUT_DATA, 0, CM_DGAM_LUT_DATA, rgb[i].green_reg);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

699

REG_SET(CM_DGAM_LUT_DATA, 0, CM_DGAM_LUT_DATA, rgb[i].blue_reg);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

701

REG_SET(CM_DGAM_LUT_DATA, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

703

REG_SET(CM_DGAM_LUT_DATA, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

705

REG_SET(CM_DGAM_LUT_DATA, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

733

REG_SET(CNVC_SURFACE_PIXEL_FORMAT, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

744

REG_SET(CM_CONTROL, 0, CM_BYPASS_EN, 1);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

747

REG_SET(CM_DGAM_CONTROL, 0, CM_DGAM_LUT_MODE, 0);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

790

REG_SET(CM_MEM_PWR_CTRL, 0, SHARED_MEM_PWR_DIS, 1);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

813

REG_SET(CM_IGAM_LUT_SEQ_COLOR, 0, CM_IGAM_LUT_SEQ_COLOR,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

816

REG_SET(CM_IGAM_LUT_SEQ_COLOR, 0, CM_IGAM_LUT_SEQ_COLOR,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

819

REG_SET(CM_IGAM_LUT_SEQ_COLOR, 0, CM_IGAM_LUT_SEQ_COLOR,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

824

REG_SET(CM_MEM_PWR_CTRL, 0, SHARED_MEM_PWR_DIS, 0);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c

571

REG_SET(SCL_HORZ_FILTER_SCALE_RATIO, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c

574

REG_SET(SCL_VERT_FILTER_SCALE_RATIO, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c

577

REG_SET(SCL_HORZ_FILTER_SCALE_RATIO_C, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c

580

REG_SET(SCL_VERT_FILTER_SCALE_RATIO_C, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

1154

REG_SET(CURSOR_DST_OFFSET, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

356

REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

360

REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

365

REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

369

REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

385

REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

389

REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

393

REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

397

REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

402

REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

406

REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

410

REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

414

REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

436

REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

440

REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

446

REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

450

REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

455

REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

459

REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

463

REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

467

REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

558

REG_SET(BLANK_OFFSET_1, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

561

REG_SET(DST_DIMENSIONS, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

581

REG_SET(REF_FREQ_TO_PIX_FREQ, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

585

REG_SET(VBLANK_PARAMETERS_1, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

588

REG_SET(VBLANK_PARAMETERS_3, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

592

REG_SET(NOM_PARAMETERS_0, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

596

REG_SET(NOM_PARAMETERS_1, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

599

REG_SET(NOM_PARAMETERS_4, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

602

REG_SET(NOM_PARAMETERS_5, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

614

REG_SET(PREFETCH_SETTINS_C, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

617

REG_SET(PREFETCH_SETTINGS_C, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

620

REG_SET(VBLANK_PARAMETERS_2, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

623

REG_SET(VBLANK_PARAMETERS_4, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

627

REG_SET(NOM_PARAMETERS_2, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

631

REG_SET(NOM_PARAMETERS_3, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

634

REG_SET(NOM_PARAMETERS_6, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

637

REG_SET(NOM_PARAMETERS_7, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

657

REG_SET(DCN_SURF0_TTU_CNTL1, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

666

REG_SET(DCN_SURF1_TTU_CNTL1, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

674

REG_SET(DCN_CUR0_TTU_CNTL1, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

735

REG_SET(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

738

REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

740

REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

743

REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

745

REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

754

REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

756

REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

760

REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

762

REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

766

REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

768

REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

775

REG_SET(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

528

REG_SET(DC_IP_REQUEST_CNTL, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

532

REG_SET(DC_IP_REQUEST_CNTL, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

549

REG_SET(DC_IP_REQUEST_CNTL, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

553

REG_SET(DC_IP_REQUEST_CNTL, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

578

REG_SET(DC_IP_REQUEST_CNTL, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

582

REG_SET(DC_IP_REQUEST_CNTL, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

916

REG_SET(DC_IP_REQUEST_CNTL, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

921

REG_SET(DC_IP_REQUEST_CNTL, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.c

448

REG_SET(DP_CONFIG, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.c

501

REG_SET(DP_DPHY_TRAINING_PATTERN_SEL, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c

209

REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, insert_above_mpcc->mpcc_id);

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c

213

REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf);

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c

216

REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, dpp_id);

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c

217

REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, tree->opp_id);

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c

231

REG_SET(MPCC_BOT_SEL[temp_mpcc->mpcc_id], 0, MPCC_BOT_SEL, mpcc_id);

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c

297

REG_SET(MPCC_BOT_SEL[temp_mpcc->mpcc_id], 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c

301

REG_SET(MPCC_BOT_SEL[temp_mpcc->mpcc_id], 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c

311

REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf);

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c

312

REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf);

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c

313

REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, 0xf);

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c

321

REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf);

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c

322

REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf);

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c

323

REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, 0xf);

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c

354

REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf);

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c

355

REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf);

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c

356

REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, 0xf);

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c

54

REG_SET(MPCC_BG_R_CR[mpcc_id], 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c

56

REG_SET(MPCC_BG_G_Y[mpcc_id], 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c

58

REG_SET(MPCC_BG_B_CB[mpcc_id], 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_opp.c

102

REG_SET(FMT_DITHER_RAND_B_SEED, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_opp.c

96

REG_SET(FMT_DITHER_RAND_R_SEED, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_opp.c

99

REG_SET(FMT_DITHER_RAND_G_SEED, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

198

REG_SET(OTG_H_TOTAL, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

237

REG_SET(OTG_V_TOTAL, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

243

REG_SET(OTG_V_TOTAL_MAX, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

245

REG_SET(OTG_V_TOTAL_MIN, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

281

REG_SET(OTG_VERTICAL_INTERRUPT2_POSITION, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

601

REG_SET(OTG_GLOBAL_CONTROL0, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

603

REG_SET(OTG_MASTER_UPDATE_LOCK, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

617

REG_SET(OTG_MASTER_UPDATE_LOCK, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

669

REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

672

REG_SET(OTG_VERT_SYNC_CONTROL, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

703

REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

72

REG_SET(OTG_VSTARTUP_PARAM, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

742

REG_SET(OTG_VERT_SYNC_CONTROL, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

746

REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

79

REG_SET(OTG_VREADY_PARAM, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

827

REG_SET(OTG_V_TOTAL_MAX, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

830

REG_SET(OTG_V_TOTAL_MIN, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

846

REG_SET(OTG_V_TOTAL_MIN, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

849

REG_SET(OTG_V_TOTAL_MAX, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

87

REG_SET(OTG_STEREO_CONTROL, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

1174

REG_SET(AFMT_AUDIO_SRC_CONTROL, 0, AFMT_AUDIO_SRC_SELECT, az_inst);

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

1271

REG_SET(DP_SEC_AUD_N, 0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

1275

REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE,

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

410

REG_SET(DP_MSA_COLORIMETRY, 0, DP_MSA_MISC0, misc0);

sys/dev/drm/amd/display/dc/gpio/hw_ddc.c

113

REG_SET(gpio.MASK_reg, regval,

sys/dev/drm/amd/display/dc/gpio/hw_ddc.c

122

REG_SET(gpio.MASK_reg, regval,

sys/dev/drm/amd/display/dc/gpio/hw_ddc.c

151

REG_SET(gpio.MASK_reg, regval,

sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c

250

value = REG_SET(AUX_SW_DATA, value,

sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c

254

value = REG_SET(AUX_SW_DATA, value,

sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c

266

value = REG_SET(AUX_SW_DATA, value,

sys/dev/drm/amd/display/dc/inc/reg_helper.h

385

REG_SET(reg, val, field, value2); }

sys/dev/drm/amd/display/dc/inc/reg_helper.h

390

REG_SET(reg, val, f2, v2); }

sys/dev/drm/amd/display/dc/inc/reg_helper.h

394

val = REG_SET(reg, val, f2, v2); \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

395

REG_SET(reg, val, f3, v3); }

sys/dev/drm/amd/display/dc/inc/reg_helper.h

45

#ifdef REG_SET

sys/dev/drm/radeon/cikd.h

1689

#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))

sys/dev/drm/radeon/evergreend.h

1541

#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))

sys/dev/drm/radeon/nid.h

1155

#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))

sys/dev/drm/radeon/r100.c

1179

tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |

sys/dev/drm/radeon/r100.c

1180

REG_SET(RADEON_RB_BLKSZ, rb_blksz) |

sys/dev/drm/radeon/r100.c

1181

REG_SET(RADEON_MAX_FETCH, max_fetch));

sys/dev/drm/radeon/r100.c

1212

REG_SET(RADEON_INDIRECT2_START, indirect2_start) |

sys/dev/drm/radeon/r100.c

1213

REG_SET(RADEON_INDIRECT1_START, indirect1_start));

sys/dev/drm/radeon/r100d.h

60

REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \

sys/dev/drm/radeon/r100d.h

61

REG_SET(PACKET0_COUNT, (n)))

sys/dev/drm/radeon/r100d.h

62

#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))

sys/dev/drm/radeon/r100d.h

64

REG_SET(PACKET3_IT_OPCODE, (op)) | \

sys/dev/drm/radeon/r100d.h

65

REG_SET(PACKET3_COUNT, (n)))

sys/dev/drm/radeon/r300d.h

61

REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \

sys/dev/drm/radeon/r300d.h

62

REG_SET(PACKET0_COUNT, (n)))

sys/dev/drm/radeon/r300d.h

63

#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))

sys/dev/drm/radeon/r300d.h

65

REG_SET(PACKET3_IT_OPCODE, (op)) | \

sys/dev/drm/radeon/r300d.h

66

REG_SET(PACKET3_COUNT, (n)))

sys/dev/drm/radeon/r600d.h

34

#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))

sys/dev/drm/radeon/rs400.c

147

tmp = REG_SET(RS690_MC_AGP_TOP, rdev->mc.gtt_end >> 16);

sys/dev/drm/radeon/rs400.c

148

tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_start >> 16);

sys/dev/drm/radeon/rv515d.h

201

REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \

sys/dev/drm/radeon/rv515d.h

202

REG_SET(PACKET0_COUNT, (n)))

sys/dev/drm/radeon/rv515d.h

203

#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))

sys/dev/drm/radeon/rv515d.h

205

REG_SET(PACKET3_IT_OPCODE, (op)) | \

sys/dev/drm/radeon/rv515d.h

206

REG_SET(PACKET3_COUNT, (n)))

sys/dev/drm/radeon/sid.h

1593

#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))