sys/dev/drm/amd/display/dc/bios/bios_parser_helper.c

87

active_disp = REG_READ(BIOS_SCRATCH_3) & 0XFFFF;

sys/dev/drm/amd/display/dc/dce/dce_abm.c

237

s2 = REG_READ(BIOS_SCRATCH_2);

sys/dev/drm/amd/display/dc/dce/dce_abm.c

294

unsigned int backlight = REG_READ(BL1_PWM_CURRENT_ABM_LEVEL);

sys/dev/drm/amd/display/dc/dce/dce_abm.c

333

REG_READ(BL_PWM_CNTL);

sys/dev/drm/amd/display/dc/dce/dce_abm.c

335

REG_READ(BL_PWM_CNTL2);

sys/dev/drm/amd/display/dc/dce/dce_abm.c

337

REG_READ(BL_PWM_PERIOD_CNTL);

sys/dev/drm/amd/display/dc/dce/dce_abm.c

375

REG_READ(BL_PWM_CNTL);

sys/dev/drm/amd/display/dc/dce/dce_abm.c

377

REG_READ(BL_PWM_CNTL2);

sys/dev/drm/amd/display/dc/dce/dce_abm.c

379

REG_READ(BL_PWM_PERIOD_CNTL);

sys/dev/drm/amd/display/dc/dce/dce_abm.c

389

value = REG_READ(BIOS_SCRATCH_2);

sys/dev/drm/amd/display/dc/dce/dce_abm.c

65

pwm_period_cntl = REG_READ(BL_PWM_PERIOD_CNTL);

sys/dev/drm/amd/display/dc/dce/dce_abm.c

69

bl_pwm_cntl = REG_READ(BL_PWM_CNTL);

sys/dev/drm/amd/display/dc/dce/dce_audio.c

84

value = REG_READ(AZALIA_F0_CODEC_ENDPOINT_DATA);

sys/dev/drm/amd/display/dc/dce/dce_aux.c

139

value = REG_READ(AUX_ARB_CONTROL);

sys/dev/drm/amd/display/dc/dce/dce_aux.c

73

uint32_t value = REG_READ(AUX_ARB_CONTROL);

sys/dev/drm/amd/display/dc/dce/dce_aux.c

86

uint32_t value = REG_READ(AUX_ARB_CONTROL);

sys/dev/drm/amd/display/dc/dce/dce_aux.c

94

value = REG_READ(AUX_CONTROL);

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

107

*psr_state = REG_READ(DMCU_IRAM_RD_DATA);

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

337

dmcu->dmcu_state = REG_READ(DMCU_IRAM_RD_DATA);

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

362

dmcu->dmcu_version.interface_version = REG_READ(DMCU_IRAM_RD_DATA);

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

363

dmcu->dmcu_version.year = ((REG_READ(DMCU_IRAM_RD_DATA) << 8) |

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

364

REG_READ(DMCU_IRAM_RD_DATA));

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

365

dmcu->dmcu_version.month = REG_READ(DMCU_IRAM_RD_DATA);

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

366

dmcu->dmcu_version.date = REG_READ(DMCU_IRAM_RD_DATA);

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

390

if (dmcu->dmcu_version.interface_version != REG_READ(DC_DMCU_SCRATCH))

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

399

if (REG_READ(DC_DMCU_SCRATCH) == 0)

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

506

*psr_state = REG_READ(DMCU_IRAM_RD_DATA);

sys/dev/drm/amd/display/dc/dce/dce_hwseq.c

82

uint32_t value = REG_READ(CRTC_H_BLANK_START_END[pipe->stream_res.tg->inst]);

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c

1330

value0 = REG_READ(DP_MSE_SAT_UPDATE);

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c

267

value = REG_READ(DP_DPHY_INTERNAL_CTRL);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

100

regval = REG_READ(AFMT_VBI_PACKET_CONTROL);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

1516

value = REG_READ(DP_SEC_CNTL);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

333

misc1 = REG_READ(DP_MSA_MISC);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

875

value = REG_READ(DP_SEC_CNTL);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

901

value = REG_READ(DP_SEC_CNTL);

sys/dev/drm/amd/display/dc/dce/dce_transform.c

198

power_ctl = REG_READ(DCFE_MEM_PWR_CTRL);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c

120

s->gamut_remap_c11_c12 = REG_READ(CM_GAMUT_REMAP_C11_C12);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c

121

s->gamut_remap_c13_c14 = REG_READ(CM_GAMUT_REMAP_C13_C14);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c

122

s->gamut_remap_c21_c22 = REG_READ(CM_GAMUT_REMAP_C21_C22);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c

123

s->gamut_remap_c23_c24 = REG_READ(CM_GAMUT_REMAP_C23_C24);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c

124

s->gamut_remap_c31_c32 = REG_READ(CM_GAMUT_REMAP_C31_C32);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c

125

s->gamut_remap_c33_c34 = REG_READ(CM_GAMUT_REMAP_C33_C34);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c

348

uint32_t scl_mode = REG_READ(SCL_MODE);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

199

debug_data = REG_READ(DCHUBBUB_TEST_DEBUG_DATA);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

51

s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

52

s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

54

s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

55

s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

57

s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

61

s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

62

s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

64

s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

65

s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

67

s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

71

s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

72

s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

74

s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

75

s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

77

s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

81

s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

82

s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

84

s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

85

s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

87

s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

1140

if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

117

value = REG_READ(HUBPREQ_DEBUG_DB);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

51

uint32_t reg_val = REG_READ(DCHUBP_CNTL);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

86

REG_READ(MPC_CRC_RESULT_GB), REG_READ(MPC_CRC_RESULT_C), REG_READ(MPC_CRC_RESULT_AR));

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

89

REG_READ(DPP_TOP0_DPP_CRC_VAL_B_A), REG_READ(DPP_TOP0_DPP_CRC_VAL_R_G));

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.c

1249

value0 = REG_READ(DP_MSE_SAT_UPDATE);

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.c

232

value = REG_READ(DP_DPHY_INTERNAL_CTRL);

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

1354

value = REG_READ(DP_SEC_CNTL);

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

296

misc1 = REG_READ(DP_MSA_MISC);

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

732

value = REG_READ(DP_SEC_CNTL);

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

759

value = REG_READ(DP_SEC_CNTL);

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

89

regval = REG_READ(AFMT_VBI_PACKET_CONTROL);

sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c

104

uint32_t value = REG_READ(AUX_ARB_CONTROL);

sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c

117

uint32_t value = REG_READ(AUX_ARB_CONTROL);

sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c

125

value = REG_READ(AUX_CONTROL);

sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c

170

value = REG_READ(AUX_ARB_CONTROL);

sys/dev/drm/amd/display/dc/inc/reg_helper.h

228

REG_READ(reg_name), \