Symbol: REG_GET_FIELD
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
114
config->num_banks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
116
config->num_ranks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
605
if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, PROCESSING_IQ)) {
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
609
if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, ACTIVE)) {
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
610
if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, RETRY_TYPE)
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
617
if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, WAIT_TIME)
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
463
2 << REG_GET_FIELD(m->cp_hqd_pq_control,
sys/dev/drm/amd/amdgpu/cz_ih.c
194
if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) {
sys/dev/drm/amd/amdgpu/cz_ih.c
360
if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
sys/dev/drm/amd/amdgpu/cz_ih.c
375
if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
sys/dev/drm/amd/amdgpu/dce_v10_0.c
408
if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) {
sys/dev/drm/amd/amdgpu/dce_v10_0.c
478
crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
sys/dev/drm/amd/amdgpu/dce_v10_0.c
625
if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED))
sys/dev/drm/amd/amdgpu/dce_v10_0.c
659
switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
sys/dev/drm/amd/amdgpu/dce_v11_0.c
424
if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) {
sys/dev/drm/amd/amdgpu/dce_v11_0.c
504
crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
sys/dev/drm/amd/amdgpu/dce_v11_0.c
651
if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED))
sys/dev/drm/amd/amdgpu/dce_v11_0.c
685
switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
sys/dev/drm/amd/amdgpu/dce_v8_0.c
418
crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4416
dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4417
dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4420
dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4421
dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
1932
dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
1933
dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
1936
dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
1937
dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
1956
tmp = REG_GET_FIELD(mc_arb_ramcfg, MC_ARB_RAMCFG, NOOFCOLS);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
3557
data = REG_GET_FIELD(data, GC_USER_RB_BACKEND_DISABLE, BACKEND_DISABLE);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4915
if (REG_GET_FIELD(RREG32(mmGRBM_STATUS), GRBM_STATUS, GUI_ACTIVE)
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5026
if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5030
if (REG_GET_FIELD(tmp, GRBM_STATUS2, CPF_BUSY) ||
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5031
REG_GET_FIELD(tmp, GRBM_STATUS2, CPC_BUSY) ||
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5032
REG_GET_FIELD(tmp, GRBM_STATUS2, CPG_BUSY)) {
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5045
if (REG_GET_FIELD(tmp, SRBM_STATUS, GRBM_RQ_PENDING))
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5048
if (REG_GET_FIELD(tmp, SRBM_STATUS, SEM_BUSY))
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5078
if (REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP) ||
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5079
REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_GFX))
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5083
if (REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP) ||
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5084
REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPF) ||
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5085
REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPC) ||
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5086
REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPG)) {
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5179
if (REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP) ||
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5180
REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPF) ||
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5181
REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPC) ||
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5182
REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPG)) {
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5198
if (REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP) ||
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5199
REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_GFX))
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5624
if (!REG_GET_FIELD(RREG32(mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5651
if (!REG_GET_FIELD(RREG32(mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
6775
enc = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_CMN, ENCODING);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
6776
se_id = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_CMN, SE_ID);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
6786
REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, IMMED_OVERFLOW),
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
6787
REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, HOST_REG_OVERFLOW),
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
6788
REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, HOST_CMD_OVERFLOW),
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
6789
REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, CMD_TIMESTAMP),
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
6790
REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, REG_TIMESTAMP),
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
6791
REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, THREAD_TRACE_BUF_FULL),
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
6792
REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, WLT),
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
6793
REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, THREAD_TRACE)
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
6799
cu_id = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, CU_ID);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
6800
sh_id = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, SH_ID);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
6811
sq_edc_source = REG_GET_FIELD(RREG32(mmSQ_EDC_INFO), SQ_EDC_INFO, SOURCE);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
6827
REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, SIMD_ID),
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
6828
REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, WAVE_ID),
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
6829
REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, VM_ID),
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
6830
REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, PRIV) ? "true" : "false",
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
7103
return ~REG_GET_FIELD(data, CC_GC_SHADER_ARRAY_CONFIG, INACTIVE_CUS) & mask;
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
1445
REG_GET_FIELD(
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
1454
REG_GET_FIELD(
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
1459
REG_GET_FIELD(
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
1464
REG_GET_FIELD(
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
1469
REG_GET_FIELD(
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
1474
REG_GET_FIELD(
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
3459
if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
3506
if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
3634
if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
sys/dev/drm/amd/amdgpu/gfxhub_v1_1.c
35
REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL, PF_MAX_REGION);
sys/dev/drm/amd/amdgpu/gfxhub_v1_1.c
44
REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL, PF_LFB_REGION);
sys/dev/drm/amd/amdgpu/gfxhub_v1_1.c
47
adev->gmc.xgmi.node_segment_size = REG_GET_FIELD(
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
1314
vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
1319
u32 protections = REG_GET_FIELD(status,
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
1324
info->mc_id = REG_GET_FIELD(status,
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
200
running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
223
if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
229
if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
330
if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) {
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
336
switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
766
u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
767
u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
773
mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
778
REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
94
if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
966
if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
970
size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
971
REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) *
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1010
u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1011
u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1017
mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1022
REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1084
if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1088
size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1089
REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) *
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1498
vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1503
u32 protections = REG_GET_FIELD(status,
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1508
info->mc_id = REG_GET_FIELD(status,
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
182
if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
325
running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
348
if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
354
if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
532
if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) {
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
538
switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
sys/dev/drm/amd/amdgpu/gmc_v9_0.c
636
field_val = REG_GET_FIELD(reg_val, UMCCH0_0_UmcLocalCap,
sys/dev/drm/amd/amdgpu/gmc_v9_0.c
654
field_val = REG_GET_FIELD(reg_val, UMCCH0_0_UMC_CONFIG,
sys/dev/drm/amd/amdgpu/gmc_v9_0.c
673
field_val = REG_GET_FIELD(reg_val, UMCCH0_0_EccCtrl,
sys/dev/drm/amd/amdgpu/gmc_v9_0.c
675
fv2 = REG_GET_FIELD(reg_val, UMCCH0_0_EccCtrl,
sys/dev/drm/amd/amdgpu/gmc_v9_0.c
893
if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
sys/dev/drm/amd/amdgpu/gmc_v9_0.c
901
size = (REG_GET_FIELD(viewport,
sys/dev/drm/amd/amdgpu/gmc_v9_0.c
903
REG_GET_FIELD(viewport,
sys/dev/drm/amd/amdgpu/gmc_v9_0.c
912
size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
sys/dev/drm/amd/amdgpu/gmc_v9_0.c
913
REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH) *
sys/dev/drm/amd/amdgpu/iceland_ih.c
194
if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) {
sys/dev/drm/amd/amdgpu/iceland_ih.c
360
if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
sys/dev/drm/amd/amdgpu/iceland_ih.c
375
if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
1294
if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) ||
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
1295
REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) {
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
1313
if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) ||
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
1314
REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) {
sys/dev/drm/amd/amdgpu/tonga_ih.c
205
if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) {
sys/dev/drm/amd/amdgpu/tonga_ih.c
383
if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
sys/dev/drm/amd/amdgpu/tonga_ih.c
398
if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
1147
if (REG_GET_FIELD(tmp, SRBM_STATUS, UVD_RQ_PENDING) ||
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
1148
REG_GET_FIELD(tmp, SRBM_STATUS, UVD_BUSY) ||
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
1466
if (REG_GET_FIELD(tmp, SRBM_STATUS, UVD_RQ_PENDING) ||
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
1467
REG_GET_FIELD(tmp, SRBM_STATUS, UVD_BUSY) ||
sys/dev/drm/amd/amdgpu/vega10_ih.c
203
if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) {
sys/dev/drm/amd/amdgpu/vi.c
335
if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK))
sys/dev/drm/amd/amdgpu/vi.c
339
if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL, XTALIN_DIVIDE))
sys/dev/drm/amd/amdgpu/vi.c
458
if (REG_GET_FIELD(reg, BIF_IOV_FUNC_IDENTIFIER, FUNC_IDENTIFIER))
sys/dev/drm/amd/amdgpu/vi.c
461
if (REG_GET_FIELD(reg, BIF_IOV_FUNC_IDENTIFIER, IOV_ENABLE))
sys/dev/drm/amd/powerplay/hwmgr/vega10_thermal.c
106
REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_STATUS),
sys/dev/drm/amd/powerplay/hwmgr/vega10_thermal.c
134
REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
sys/dev/drm/amd/powerplay/hwmgr/vega10_thermal.c
137
REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
sys/dev/drm/amd/powerplay/hwmgr/vega10_thermal.c
268
duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
sys/dev/drm/amd/powerplay/hwmgr/vega20_thermal.c
150
duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),