sys/dev/drm/amd/amdgpu/amdgpu.h

1151

(((orig_val) & ~REG_FIELD_MASK(reg, field)) | \

sys/dev/drm/amd/amdgpu/amdgpu.h

1152

(REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))

sys/dev/drm/amd/amdgpu/amdgpu.h

1155

(((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))

sys/dev/drm/amd/amdgpu/amdgpu.h

1158

WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))

sys/dev/drm/amd/amdgpu/amdgpu.h

1161

WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))

sys/dev/drm/amd/amdgpu/mxgpu_vi.c

322

u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL, RCV_MSG_VALID);

sys/dev/drm/amd/amdgpu/mxgpu_vi.c

369

u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL, RCV_MSG_VALID);

sys/dev/drm/amd/amdgpu/mxgpu_vi.c

391

u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL, TRN_MSG_ACK);

sys/dev/drm/amd/amdgpu/soc15_common.h

33

& ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))