sys/bus/pci/pci.c

3087

hdrtype = REG(PCIR_HDRTYPE, 1);

sys/bus/pci/pci.c

513

cfg->subvendor = REG(PCIR_SUBVEND_0, 2);

sys/bus/pci/pci.c

514

cfg->subdevice = REG(PCIR_SUBDEV_0, 2);

sys/bus/pci/pci.c

521

cfg->subvendor = REG(PCIR_SUBVEND_2, 2);

sys/bus/pci/pci.c

522

cfg->subdevice = REG(PCIR_SUBDEV_2, 2);

sys/bus/pci/pci.c

542

if (REG(PCIR_DEVVENDOR, 4) != -1) {

sys/bus/pci/pci.c

551

cfg->vendor = REG(PCIR_VENDOR, 2);

sys/bus/pci/pci.c

552

cfg->device = REG(PCIR_DEVICE, 2);

sys/bus/pci/pci.c

553

cfg->cmdreg = REG(PCIR_COMMAND, 2);

sys/bus/pci/pci.c

554

cfg->statreg = REG(PCIR_STATUS, 2);

sys/bus/pci/pci.c

555

cfg->baseclass = REG(PCIR_CLASS, 1);

sys/bus/pci/pci.c

556

cfg->subclass = REG(PCIR_SUBCLASS, 1);

sys/bus/pci/pci.c

557

cfg->progif = REG(PCIR_PROGIF, 1);

sys/bus/pci/pci.c

558

cfg->revid = REG(PCIR_REVID, 1);

sys/bus/pci/pci.c

559

cfg->hdrtype = REG(PCIR_HDRTYPE, 1);

sys/bus/pci/pci.c

560

cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1);

sys/bus/pci/pci.c

561

cfg->lattimer = REG(PCIR_LATTIMER, 1);

sys/bus/pci/pci.c

562

cfg->intpin = REG(PCIR_INTPIN, 1);

sys/bus/pci/pci.c

563

cfg->intline = REG(PCIR_INTLINE, 1);

sys/bus/pci/pci.c

565

cfg->mingnt = REG(PCIR_MINGNT, 1);

sys/bus/pci/pci.c

566

cfg->maxlat = REG(PCIR_MAXLAT, 1);

sys/bus/pci/pci.c

647

pp->pp_cap = REG(ptr + PCIR_POWER_CAP, 2);

sys/bus/pci/pci.c

681

val = REG(ptr + PCIR_HT_COMMAND, 2);

sys/bus/pci/pci.c

691

addr = REG(ptr + PCIR_HTMSI_ADDRESS_HI, 4);

sys/bus/pci/pci.c

693

addr |= REG(ptr + PCIR_HTMSI_ADDRESS_LO, 4);

sys/bus/pci/pci.c

722

msi->msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2);

sys/bus/pci/pci.c

738

msix->msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2);

sys/bus/pci/pci.c

741

val = REG(ptr + PCIR_MSIX_TABLE, 4);

sys/bus/pci/pci.c

745

val = REG(ptr + PCIR_MSIX_PBA, 4);

sys/bus/pci/pci.c

770

val = REG(ptr + PCIR_SUBVENDCAP_ID, 4);

sys/bus/pci/pci.c

835

expr->expr_cap = REG(ptr + PCIER_CAPABILITY, 2);

sys/bus/pci/pci.c

842

expr->expr_slotcap = REG(ptr + PCIER_SLOTCAP, 4);

sys/bus/pci/pci.c

856

if ((REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) == 0) {

sys/bus/pci/pci.c

872

nextptr = REG(ptrptr, 1); /* sanity check? */

sys/bus/pci/pci.c

882

nextptr = REG(ptr + PCICAP_NEXTPTR, 1);

sys/bus/pci/pci.c

885

val = REG(ptr + PCICAP_ID, 1);

sys/bus/pci/pci.c

929

while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) != 0x8000) {

sys/bus/pci/pci.c

934

*data = (REG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, 4));

sys/bus/pci/pci.c

949

while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) == 0x8000) {

sys/dev/disk/ncr/ncr.c

1371

#define RADDR(label) (RELOC_REGISTER | REG(label))

sys/dev/disk/ncr/ncr.c

1372

#define FADDR(label,ofs)(RELOC_REGISTER | ((REG(label))+(ofs)))

sys/dev/disk/ncr/ncrreg.h

426

(0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | ((data)<<8ul))

sys/dev/disk/ncr/ncrreg.h

429

(0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | ((data)<<8ul))

sys/dev/disk/ncr/ncrreg.h

432

(0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | ((data)<<8ul))

sys/dev/disk/sym/sym_defs.h

729

(0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))

sys/dev/disk/sym/sym_defs.h

732

(0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))

sys/dev/disk/sym/sym_defs.h

735

(0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))

sys/dev/disk/sym/sym_defs.h

801

(0xe1000000 | (how) | (SCR_REG_OFS2(REG(reg))) | (n))

sys/dev/disk/sym/sym_defs.h

804

(0xe0000000 | (how) | (SCR_REG_OFS2(REG(reg))) | (n))

sys/dev/disk/sym/sym_fw.h

200

#define RADDR_1(label) (RELOC_REGISTER | REG(label))

sys/dev/disk/sym/sym_fw.h

201

#define RADDR_2(label,ofs) (RELOC_REGISTER | ((REG(label))+(ofs)))

sys/dev/drm/amd/display/dc/dce/dce_aux.c

106

if (REG(AUX_RESET_MASK)) {

sys/dev/drm/amd/display/dc/dce/dce_aux.c

117

if (REG(AUX_RESET_MASK)) {

sys/dev/drm/amd/display/dc/dce/dce_aux.c

171

if (REG(AUXN_IMPCAL)) {

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

239

dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1),

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

251

dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2),

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

256

dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3),

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

304

dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32);

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

658

dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1),

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

670

dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2),

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

675

dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3),

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

709

dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32);

sys/dev/drm/amd/display/dc/dce/dce_hwseq.c

111

if (REG(BLND_CONTROL[blnd_inst]) == REG(BLNDV_CONTROL) ||

sys/dev/drm/amd/display/dc/dce/dce_hwseq.c

131

if (REG(DC_MEM_GLOBAL_PWR_REQ_CNTL))

sys/dev/drm/amd/display/dc/dce/dce_hwseq.c

139

if (REG(DCFEV_CLOCK_CONTROL))

sys/dev/drm/amd/display/dc/dce/dce_hwseq.c

191

if (REG(PHYPLL_PIXEL_RATE_CNTL[tg_inst]))

sys/dev/drm/amd/display/dc/dce/dce_ipp.c

177

if (REG(DCFE_MEM_PWR_CTRL))

sys/dev/drm/amd/display/dc/dce/dce_ipp.c

209

if (REG(DCFE_MEM_PWR_CTRL))

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c

266

ASSERT(REG(DP_DPHY_INTERNAL_CTRL));

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c

407

if (REG(DP_DPHY_HBR2_PATTERN_CONTROL))

sys/dev/drm/amd/display/dc/dce/dce_mem_input.c

201

if (REG(DPG_PIPE_NB_PSTATE_CHANGE_CONTROL)) {

sys/dev/drm/amd/display/dc/dce/dce_mem_input.c

214

if (REG(DPG_PIPE_LOW_POWER_CONTROL)) {

sys/dev/drm/amd/display/dc/dce/dce_mem_input.c

237

if (REG(DPG_PIPE_STUTTER_CONTROL2))

sys/dev/drm/amd/display/dc/dce/dce_mem_input.c

255

if (REG(DPG_PIPE_STUTTER_CONTROL2))

sys/dev/drm/amd/display/dc/dce/dce_opp.c

293

if (REG(FMT_TEMPORAL_DITHER_PATTERN_CONTROL)) {

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

132

if (!REG(AFMT_VBI_PACKET_CONTROL1)) {

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

139

if (REG(AFMT_VBI_PACKET_CONTROL1)) {

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

1467

if (REG(AFMT_CNTL) == 0)

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

234

if (REG(HDMI_GENERIC_PACKET_CONTROL2))

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

241

if (REG(HDMI_GENERIC_PACKET_CONTROL2))

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

248

if (REG(HDMI_GENERIC_PACKET_CONTROL3))

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

255

if (REG(HDMI_GENERIC_PACKET_CONTROL3))

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

332

if (REG(DP_MSA_MISC))

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

387

if (REG(DP_MSA_TIMING_PARAM1)) {

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

445

if (REG(DP_MSA_COLORIMETRY))

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

448

if (REG(DP_MSA_MISC))

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

454

if (REG(DP_MSA_TIMING_PARAM1))

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

481

if (REG(DP_MSA_TIMING_PARAM2))

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

486

if (REG(DP_MSA_TIMING_PARAM3))

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

498

if (REG(DP_MSA_TIMING_PARAM4))

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

740

if (REG(AFMT_CNTL))

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

75

if (REG(AFMT_CNTL))

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

779

if (REG(HDMI_DB_CONTROL))

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

78

if (REG(AFMT_VBI_PACKET_CONTROL1)) {

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

816

if (REG(HDMI_GENERIC_PACKET_CONTROL2))

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

825

if (REG(HDMI_GENERIC_PACKET_CONTROL3))

sys/dev/drm/amd/display/dc/dce/dce_transform.c

1147

if (REG(DCFE_MEM_PWR_CTRL))

sys/dev/drm/amd/display/dc/dce/dce_transform.c

1155

if (REG(DCFE_MEM_PWR_STATUS)) {

sys/dev/drm/amd/display/dc/dce/dce_transform.c

1201

if (REG(DCFE_MEM_PWR_CTRL))

sys/dev/drm/amd/display/dc/dce/dce_transform.c

1305

if (REG(DCFE_MEM_PWR_CTRL))

sys/dev/drm/amd/display/dc/dce/dce_transform.c

197

if (REG(DCFE_MEM_PWR_CTRL)) {

sys/dev/drm/amd/display/dc/dce/dce_transform.c

231

if (REG(DCFE_MEM_PWR_CTRL))

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

156

gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_C11_C12);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

157

gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_C33_C34);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

166

gam_regs.csc_c11_c12 = REG(CM_COMA_C11_C12);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

167

gam_regs.csc_c33_c34 = REG(CM_COMA_C33_C34);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

176

gam_regs.csc_c11_c12 = REG(CM_COMB_C11_C12);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

177

gam_regs.csc_c33_c34 = REG(CM_COMB_C33_C34);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

251

gam_regs.csc_c11_c12 = REG(CM_OCSC_C11_C12);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

252

gam_regs.csc_c33_c34 = REG(CM_OCSC_C33_C34);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

256

gam_regs.csc_c11_c12 = REG(CM_COMB_C11_C12);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

257

gam_regs.csc_c33_c34 = REG(CM_COMB_C33_C34);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

402

gam_regs.start_cntl_b = REG(CM_RGAM_RAMA_START_CNTL_B);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

403

gam_regs.start_cntl_g = REG(CM_RGAM_RAMA_START_CNTL_G);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

404

gam_regs.start_cntl_r = REG(CM_RGAM_RAMA_START_CNTL_R);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

405

gam_regs.start_slope_cntl_b = REG(CM_RGAM_RAMA_SLOPE_CNTL_B);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

406

gam_regs.start_slope_cntl_g = REG(CM_RGAM_RAMA_SLOPE_CNTL_G);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

407

gam_regs.start_slope_cntl_r = REG(CM_RGAM_RAMA_SLOPE_CNTL_R);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

408

gam_regs.start_end_cntl1_b = REG(CM_RGAM_RAMA_END_CNTL1_B);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

409

gam_regs.start_end_cntl2_b = REG(CM_RGAM_RAMA_END_CNTL2_B);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

410

gam_regs.start_end_cntl1_g = REG(CM_RGAM_RAMA_END_CNTL1_G);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

411

gam_regs.start_end_cntl2_g = REG(CM_RGAM_RAMA_END_CNTL2_G);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

412

gam_regs.start_end_cntl1_r = REG(CM_RGAM_RAMA_END_CNTL1_R);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

413

gam_regs.start_end_cntl2_r = REG(CM_RGAM_RAMA_END_CNTL2_R);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

414

gam_regs.region_start = REG(CM_RGAM_RAMA_REGION_0_1);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

415

gam_regs.region_end = REG(CM_RGAM_RAMA_REGION_32_33);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

431

gam_regs.start_cntl_b = REG(CM_RGAM_RAMB_START_CNTL_B);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

432

gam_regs.start_cntl_g = REG(CM_RGAM_RAMB_START_CNTL_G);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

433

gam_regs.start_cntl_r = REG(CM_RGAM_RAMB_START_CNTL_R);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

434

gam_regs.start_slope_cntl_b = REG(CM_RGAM_RAMB_SLOPE_CNTL_B);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

435

gam_regs.start_slope_cntl_g = REG(CM_RGAM_RAMB_SLOPE_CNTL_G);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

436

gam_regs.start_slope_cntl_r = REG(CM_RGAM_RAMB_SLOPE_CNTL_R);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

437

gam_regs.start_end_cntl1_b = REG(CM_RGAM_RAMB_END_CNTL1_B);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

438

gam_regs.start_end_cntl2_b = REG(CM_RGAM_RAMB_END_CNTL2_B);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

439

gam_regs.start_end_cntl1_g = REG(CM_RGAM_RAMB_END_CNTL1_G);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

440

gam_regs.start_end_cntl2_g = REG(CM_RGAM_RAMB_END_CNTL2_G);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

441

gam_regs.start_end_cntl1_r = REG(CM_RGAM_RAMB_END_CNTL1_R);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

442

gam_regs.start_end_cntl2_r = REG(CM_RGAM_RAMB_END_CNTL2_R);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

443

gam_regs.region_start = REG(CM_RGAM_RAMB_REGION_0_1);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

444

gam_regs.region_end = REG(CM_RGAM_RAMB_REGION_32_33);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

505

gam_regs.csc_c11_c12 = REG(CM_ICSC_C11_C12);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

506

gam_regs.csc_c33_c34 = REG(CM_ICSC_C33_C34);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

510

gam_regs.csc_c11_c12 = REG(CM_COMA_C11_C12);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

511

gam_regs.csc_c33_c34 = REG(CM_COMA_C33_C34);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

555

gam_regs.start_cntl_b = REG(CM_DGAM_RAMB_START_CNTL_B);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

556

gam_regs.start_cntl_g = REG(CM_DGAM_RAMB_START_CNTL_G);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

557

gam_regs.start_cntl_r = REG(CM_DGAM_RAMB_START_CNTL_R);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

558

gam_regs.start_slope_cntl_b = REG(CM_DGAM_RAMB_SLOPE_CNTL_B);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

559

gam_regs.start_slope_cntl_g = REG(CM_DGAM_RAMB_SLOPE_CNTL_G);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

560

gam_regs.start_slope_cntl_r = REG(CM_DGAM_RAMB_SLOPE_CNTL_R);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

561

gam_regs.start_end_cntl1_b = REG(CM_DGAM_RAMB_END_CNTL1_B);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

562

gam_regs.start_end_cntl2_b = REG(CM_DGAM_RAMB_END_CNTL2_B);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

563

gam_regs.start_end_cntl1_g = REG(CM_DGAM_RAMB_END_CNTL1_G);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

564

gam_regs.start_end_cntl2_g = REG(CM_DGAM_RAMB_END_CNTL2_G);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

565

gam_regs.start_end_cntl1_r = REG(CM_DGAM_RAMB_END_CNTL1_R);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

566

gam_regs.start_end_cntl2_r = REG(CM_DGAM_RAMB_END_CNTL2_R);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

567

gam_regs.region_start = REG(CM_DGAM_RAMB_REGION_0_1);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

568

gam_regs.region_end = REG(CM_DGAM_RAMB_REGION_14_15);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

584

gam_regs.start_cntl_b = REG(CM_DGAM_RAMA_START_CNTL_B);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

585

gam_regs.start_cntl_g = REG(CM_DGAM_RAMA_START_CNTL_G);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

586

gam_regs.start_cntl_r = REG(CM_DGAM_RAMA_START_CNTL_R);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

587

gam_regs.start_slope_cntl_b = REG(CM_DGAM_RAMA_SLOPE_CNTL_B);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

588

gam_regs.start_slope_cntl_g = REG(CM_DGAM_RAMA_SLOPE_CNTL_G);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

589

gam_regs.start_slope_cntl_r = REG(CM_DGAM_RAMA_SLOPE_CNTL_R);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

590

gam_regs.start_end_cntl1_b = REG(CM_DGAM_RAMA_END_CNTL1_B);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

591

gam_regs.start_end_cntl2_b = REG(CM_DGAM_RAMA_END_CNTL2_B);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

592

gam_regs.start_end_cntl1_g = REG(CM_DGAM_RAMA_END_CNTL1_G);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

593

gam_regs.start_end_cntl2_g = REG(CM_DGAM_RAMA_END_CNTL2_G);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

594

gam_regs.start_end_cntl1_r = REG(CM_DGAM_RAMA_END_CNTL1_R);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

595

gam_regs.start_end_cntl2_r = REG(CM_DGAM_RAMA_END_CNTL2_R);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

596

gam_regs.region_start = REG(CM_DGAM_RAMA_REGION_0_1);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

597

gam_regs.region_end = REG(CM_DGAM_RAMA_REGION_14_15);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

288

if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A)) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

351

if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B)) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

414

if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C)) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

477

if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D)) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

53

if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A)) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

538

if (REG(DCHUBBUB_SDPIF_FB_TOP) == 0) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

63

if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B)) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

73

if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C)) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

83

if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D)) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

568

if (REG(PREFETCH_SETTINS))

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

591

if (REG(NOM_PARAMETERS_0))

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

595

if (REG(NOM_PARAMETERS_1))

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

613

if (REG(PREFETCH_SETTINS_C))

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

626

if (REG(NOM_PARAMETERS_2))

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

630

if (REG(NOM_PARAMETERS_3))

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

868

if (REG(PREFETCH_SETTINS))

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

891

if (REG(NOM_PARAMETERS_0))

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

895

if (REG(NOM_PARAMETERS_1))

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

913

if (REG(PREFETCH_SETTINS_C))

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

926

if (REG(NOM_PARAMETERS_2))

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

930

if (REG(NOM_PARAMETERS_3))

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

428

if (REG(DOMAIN1_PG_CONFIG) == 0)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

480

if (REG(DOMAIN0_PG_CONFIG) == 0)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

527

if (REG(DC_IP_REQUEST_CNTL)) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

84

if (REG(MPC_CRC_RESULT_GB))

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

87

if (REG(DPP_TOP0_DPP_CRC_VAL_B_A))

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

915

if (REG(DC_IP_REQUEST_CNTL)) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.c

231

ASSERT(REG(DP_DPHY_INTERNAL_CTRL));

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.c

374

if (REG(DP_DPHY_HBR2_PATTERN_CONTROL))

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c

362

if (REG(MUX[opp_id]))

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

1304

if (REG(AFMT_CNTL) == 0)

sys/dev/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

126

case REG(DC_GPIO_SYNCA_A):

sys/dev/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

141

case REG(DC_GPIO_GENLK_A):

sys/dev/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

165

case REG(DC_GPIO_DDC1_A):

sys/dev/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

168

case REG(DC_GPIO_DDC2_A):

sys/dev/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

171

case REG(DC_GPIO_DDC3_A):

sys/dev/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

174

case REG(DC_GPIO_DDC4_A):

sys/dev/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

177

case REG(DC_GPIO_DDC5_A):

sys/dev/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

180

case REG(DC_GPIO_DDC6_A):

sys/dev/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

183

case REG(DC_GPIO_DDCVGA_A):

sys/dev/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

187

case REG(DC_GPIO_I2CPAD_A):

sys/dev/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

191

case REG(DC_GPIO_PWRSEQ_A):

sys/dev/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

192

case REG(DC_GPIO_PAD_STRENGTH_1):

sys/dev/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

193

case REG(DC_GPIO_PAD_STRENGTH_2):

sys/dev/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

194

case REG(DC_GPIO_DEBUG):

sys/dev/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

215

info->offset = REG(DC_GPIO_DDC1_A);

sys/dev/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

218

info->offset = REG(DC_GPIO_DDC2_A);

sys/dev/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

221

info->offset = REG(DC_GPIO_DDC3_A);

sys/dev/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

224

info->offset = REG(DC_GPIO_DDC4_A);

sys/dev/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

227

info->offset = REG(DC_GPIO_DDC5_A);

sys/dev/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

230

info->offset = REG(DC_GPIO_DDC6_A);

sys/dev/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

233

info->offset = REG(DC_GPIO_DDCVGA_A);

sys/dev/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

236

info->offset = REG(DC_GPIO_I2CPAD_A);

sys/dev/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

247

info->offset = REG(DC_GPIO_DDC1_A);

sys/dev/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

250

info->offset = REG(DC_GPIO_DDC2_A);

sys/dev/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

253

info->offset = REG(DC_GPIO_DDC3_A);

sys/dev/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

256

info->offset = REG(DC_GPIO_DDC4_A);

sys/dev/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

259

info->offset = REG(DC_GPIO_DDC5_A);

sys/dev/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

262

info->offset = REG(DC_GPIO_DDC6_A);

sys/dev/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

265

info->offset = REG(DC_GPIO_DDCVGA_A);

sys/dev/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

268

info->offset = REG(DC_GPIO_I2CPAD_A);

sys/dev/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

276

info->offset = REG(DC_GPIO_GENERIC_A);

sys/dev/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

305

info->offset = REG(DC_GPIO_HPD_A);

sys/dev/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

333

info->offset = REG(DC_GPIO_SYNCA_A);

sys/dev/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

337

info->offset = REG(DC_GPIO_SYNCA_A);

sys/dev/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

350

info->offset = REG(DC_GPIO_GENLK_A);

sys/dev/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

354

info->offset = REG(DC_GPIO_GENLK_A);

sys/dev/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

359

info->offset = REG(DC_GPIO_GENLK_A);

sys/dev/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

363

info->offset = REG(DC_GPIO_GENLK_A);

sys/dev/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

69

case REG(DC_GPIO_GENERIC_A):

sys/dev/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

99

case REG(DC_GPIO_HPD_A):

sys/dev/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

126

case REG(DC_GPIO_SYNCA_A):

sys/dev/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

141

case REG(DC_GPIO_GENLK_A):

sys/dev/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

165

case REG(DC_GPIO_DDC1_A):

sys/dev/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

168

case REG(DC_GPIO_DDC2_A):

sys/dev/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

171

case REG(DC_GPIO_DDC3_A):

sys/dev/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

174

case REG(DC_GPIO_DDC4_A):

sys/dev/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

177

case REG(DC_GPIO_DDC5_A):

sys/dev/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

180

case REG(DC_GPIO_DDC6_A):

sys/dev/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

183

case REG(DC_GPIO_DDCVGA_A):

sys/dev/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

187

case REG(DC_GPIO_I2CPAD_A):

sys/dev/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

191

case REG(DC_GPIO_PWRSEQ_A):

sys/dev/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

192

case REG(DC_GPIO_PAD_STRENGTH_1):

sys/dev/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

193

case REG(DC_GPIO_PAD_STRENGTH_2):

sys/dev/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

194

case REG(DC_GPIO_DEBUG):

sys/dev/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

215

info->offset = REG(DC_GPIO_DDC1_A);

sys/dev/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

218

info->offset = REG(DC_GPIO_DDC2_A);

sys/dev/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

221

info->offset = REG(DC_GPIO_DDC3_A);

sys/dev/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

224

info->offset = REG(DC_GPIO_DDC4_A);

sys/dev/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

227

info->offset = REG(DC_GPIO_DDC5_A);

sys/dev/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

230

info->offset = REG(DC_GPIO_DDC6_A);

sys/dev/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

233

info->offset = REG(DC_GPIO_DDCVGA_A);

sys/dev/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

236

info->offset = REG(DC_GPIO_I2CPAD_A);

sys/dev/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

247

info->offset = REG(DC_GPIO_DDC1_A);

sys/dev/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

250

info->offset = REG(DC_GPIO_DDC2_A);

sys/dev/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

253

info->offset = REG(DC_GPIO_DDC3_A);

sys/dev/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

256

info->offset = REG(DC_GPIO_DDC4_A);

sys/dev/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

259

info->offset = REG(DC_GPIO_DDC5_A);

sys/dev/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

262

info->offset = REG(DC_GPIO_DDC6_A);

sys/dev/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

265

info->offset = REG(DC_GPIO_DDCVGA_A);

sys/dev/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

268

info->offset = REG(DC_GPIO_I2CPAD_A);

sys/dev/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

276

info->offset = REG(DC_GPIO_GENERIC_A);

sys/dev/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

305

info->offset = REG(DC_GPIO_HPD_A);

sys/dev/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

333

info->offset = REG(DC_GPIO_SYNCA_A);

sys/dev/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

337

info->offset = REG(DC_GPIO_SYNCA_A);

sys/dev/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

350

info->offset = REG(DC_GPIO_GENLK_A);

sys/dev/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

354

info->offset = REG(DC_GPIO_GENLK_A);

sys/dev/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

359

info->offset = REG(DC_GPIO_GENLK_A);

sys/dev/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

363

info->offset = REG(DC_GPIO_GENLK_A);

sys/dev/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

69

case REG(DC_GPIO_GENERIC_A):

sys/dev/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

99

case REG(DC_GPIO_HPD_A):

sys/dev/drm/amd/display/dc/gpio/ddc_regs.h

35

.type ## _reg = REG(DC_GPIO_DDC ## id ## _ ## type),\

sys/dev/drm/amd/display/dc/gpio/ddc_regs.h

49

.ddc_setup = REG(DC_I2C_DDC ## id ## _SETUP)

sys/dev/drm/amd/display/dc/gpio/ddc_regs.h

52

.type ## _reg = REG(DC_GPIO_DDCVGA_ ## type),\

sys/dev/drm/amd/display/dc/gpio/ddc_regs.h

69

.type ## _reg = REG(DC_GPIO_I2CPAD_ ## type),\

sys/dev/drm/amd/display/dc/gpio/hpd_regs.h

40

.type ## _reg = REG(DC_GPIO_HPD_## type),\

sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c

137

if (REG(AUX_RESET_MASK)) {

sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c

148

if (REG(AUX_RESET_MASK)) {

sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c

202

if (REG(AUXN_IMPCAL)) {

sys/dev/drm/amd/display/dc/inc/reg_helper.h

157

generic_reg_get(CTX, REG(reg_name), \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

161

generic_reg_get2(CTX, REG(reg_name), \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

166

generic_reg_get3(CTX, REG(reg_name), \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

172

generic_reg_get4(CTX, REG(reg_name), \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

179

generic_reg_get5(CTX, REG(reg_name), \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

187

generic_reg_get6(CTX, REG(reg_name), \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

196

generic_reg_get7(CTX, REG(reg_name), \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

206

generic_reg_get8(CTX, REG(reg_name), \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

220

REG(reg_name), FN(reg_name, field), val,\

sys/dev/drm/amd/display/dc/inc/reg_helper.h

227

REG(reg_name), \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

40

dm_read_reg(CTX, REG(reg_name))

sys/dev/drm/amd/display/dc/inc/reg_helper.h

43

dm_write_reg(CTX, REG(reg_name), value)

sys/dev/drm/amd/display/dc/inc/reg_helper.h

454

REG(index_reg_name), REG(data_reg_name), IND_REG(index), \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

465

generic_read_indirect_reg(CTX, REG(index_reg_name), REG(data_reg_name), IND_REG(index))

sys/dev/drm/amd/display/dc/inc/reg_helper.h

471

REG(index_reg_name), REG(data_reg_name), IND_REG(index), \

sys/dev/drm/amd/display/dc/inc/reg_helper.h

56

REG(reg_name), \

sys/dev/pccard/pccbb/pccbb.c

116

#define PCI_MASK_CONFIG(DEV,REG,MASK,SIZE) \

sys/dev/pccard/pccbb/pccbb.c

117

pci_write_config(DEV, REG, pci_read_config(DEV, REG, SIZE) MASK, SIZE)

sys/dev/pccard/pccbb/pccbb.c

118

#define PCI_MASK2_CONFIG(DEV,REG,MASK1,MASK2,SIZE) \

sys/dev/pccard/pccbb/pccbb.c

119

pci_write_config(DEV, REG, ( \

sys/dev/pccard/pccbb/pccbb.c

120

pci_read_config(DEV, REG, SIZE) MASK1) MASK2, SIZE)

sys/dev/pccard/pccbb/pccbb_pci.c

108

#define PCI_MASK_CONFIG(DEV,REG,MASK,SIZE) \

sys/dev/pccard/pccbb/pccbb_pci.c

109

pci_write_config(DEV, REG, pci_read_config(DEV, REG, SIZE) MASK, SIZE)

sys/dev/pccard/pccbb/pccbb_pci.c

110

#define PCI_MASK2_CONFIG(DEV,REG,MASK1,MASK2,SIZE) \

sys/dev/pccard/pccbb/pccbb_pci.c

111

pci_write_config(DEV, REG, ( \

sys/dev/pccard/pccbb/pccbb_pci.c

112

pci_read_config(DEV, REG, SIZE) MASK1) MASK2, SIZE)