sys/dev/drm/radeon/radeon_clocks.c

400

tmp = RREG32_PLL(RADEON_SCLK_CNTL);

sys/dev/drm/radeon/radeon_clocks.c

402

WREG32_PLL(RADEON_SCLK_CNTL, tmp);

sys/dev/drm/radeon/radeon_clocks.c

444

tmp = RREG32_PLL(RADEON_SCLK_CNTL);

sys/dev/drm/radeon/radeon_clocks.c

461

WREG32_PLL(RADEON_SCLK_CNTL, tmp);

sys/dev/drm/radeon/radeon_clocks.c

478

tmp = RREG32_PLL(RADEON_SCLK_CNTL);

sys/dev/drm/radeon/radeon_clocks.c

492

WREG32_PLL(RADEON_SCLK_CNTL, tmp);

sys/dev/drm/radeon/radeon_clocks.c

496

tmp = RREG32_PLL(RADEON_SCLK_CNTL);

sys/dev/drm/radeon/radeon_clocks.c

515

WREG32_PLL(RADEON_SCLK_CNTL, tmp);

sys/dev/drm/radeon/radeon_clocks.c

54

post_div = RREG32_PLL(RADEON_SCLK_CNTL) & RADEON_SCLK_SRC_SEL_MASK;

sys/dev/drm/radeon/radeon_clocks.c

552

tmp = RREG32_PLL(RADEON_SCLK_CNTL);

sys/dev/drm/radeon/radeon_clocks.c

568

WREG32_PLL(RADEON_SCLK_CNTL, tmp);

sys/dev/drm/radeon/radeon_clocks.c

633

tmp = RREG32_PLL(RADEON_SCLK_CNTL);

sys/dev/drm/radeon/radeon_clocks.c

636

WREG32_PLL(RADEON_SCLK_CNTL, tmp);

sys/dev/drm/radeon/radeon_clocks.c

665

tmp = RREG32_PLL(RADEON_SCLK_CNTL);

sys/dev/drm/radeon/radeon_clocks.c

683

WREG32_PLL(RADEON_SCLK_CNTL, tmp);

sys/dev/drm/radeon/radeon_clocks.c

738

tmp = RREG32_PLL(RADEON_SCLK_CNTL);

sys/dev/drm/radeon/radeon_clocks.c

746

WREG32_PLL(RADEON_SCLK_CNTL, tmp);

sys/dev/drm/radeon/radeon_clocks.c

749

tmp = RREG32_PLL(RADEON_SCLK_CNTL);

sys/dev/drm/radeon/radeon_clocks.c

758

WREG32_PLL(RADEON_SCLK_CNTL, tmp);

sys/dev/drm/radeon/radeon_clocks.c

793

tmp = RREG32_PLL(RADEON_SCLK_CNTL);

sys/dev/drm/radeon/radeon_clocks.c

802

WREG32_PLL(RADEON_SCLK_CNTL, tmp);

sys/dev/drm/radeon/radeon_clocks.c

838

tmp = RREG32_PLL(RADEON_SCLK_CNTL);

sys/dev/drm/radeon/radeon_clocks.c

863

WREG32_PLL(RADEON_SCLK_CNTL, tmp);