sys/dev/drm/radeon/rs780_dpm.c

148

r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_MEDIUM, 0);

sys/dev/drm/radeon/rs780_dpm.c

152

r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_MEDIUM, 0);

sys/dev/drm/radeon/rs780_dpm.c

156

r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_MEDIUM, 0);

sys/dev/drm/radeon/rs780_dpm.c

160

r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_MEDIUM, R600_DISPLAY_WATERMARK_HIGH);

sys/dev/drm/radeon/rs780_dpm.c

165

r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, false);

sys/dev/drm/radeon/rv6xx_dpm.c

1117

r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_MEDIUM,

sys/dev/drm/radeon/rv6xx_dpm.c

1119

r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_MEDIUM,

sys/dev/drm/radeon/rv6xx_dpm.c

1121

r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_MEDIUM,

sys/dev/drm/radeon/rv6xx_dpm.c

1123

r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_MEDIUM,

sys/dev/drm/radeon/rv6xx_dpm.c

1125

r600_power_level_set_pcie_gen2(rdev, R600_POWER_LEVEL_MEDIUM,

sys/dev/drm/radeon/rv6xx_dpm.c

1126

pi->hw.pcie_gen2[R600_POWER_LEVEL_MEDIUM]);

sys/dev/drm/radeon/rv6xx_dpm.c

1137

r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_MEDIUM, 1);

sys/dev/drm/radeon/rv6xx_dpm.c

1139

r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_MEDIUM,

sys/dev/drm/radeon/rv6xx_dpm.c

1141

r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_MEDIUM,

sys/dev/drm/radeon/rv6xx_dpm.c

1144

r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_MEDIUM,

sys/dev/drm/radeon/rv6xx_dpm.c

1147

rv6xx_enable_engine_spread_spectrum(rdev, R600_POWER_LEVEL_MEDIUM, false);

sys/dev/drm/radeon/rv6xx_dpm.c

1149

r600_power_level_set_pcie_gen2(rdev, R600_POWER_LEVEL_MEDIUM,

sys/dev/drm/radeon/rv6xx_dpm.c

1349

r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, true);

sys/dev/drm/radeon/rv6xx_dpm.c

1479

rv6xx_enable_engine_spread_spectrum(rdev, R600_POWER_LEVEL_MEDIUM, false);

sys/dev/drm/radeon/rv6xx_dpm.c

1594

r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, true);

sys/dev/drm/radeon/rv6xx_dpm.c

1622

r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, true);

sys/dev/drm/radeon/rv6xx_dpm.c

1632

r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, false);

sys/dev/drm/radeon/rv6xx_dpm.c

1677

r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, false);

sys/dev/drm/radeon/rv6xx_dpm.c

1706

r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, true);

sys/dev/drm/radeon/rv6xx_dpm.c

1718

r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, false);

sys/dev/drm/radeon/rv6xx_dpm.c

2148

r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, false);

sys/dev/drm/radeon/rv6xx_dpm.c

441

pi->hw.sclks[R600_POWER_LEVEL_MEDIUM] =

sys/dev/drm/radeon/rv6xx_dpm.c

447

pi->hw.medium_sclk_index = R600_POWER_LEVEL_MEDIUM;

sys/dev/drm/radeon/rv6xx_dpm.c

460

pi->hw.mclks[R600_POWER_LEVEL_MEDIUM] =

sys/dev/drm/radeon/rv6xx_dpm.c

471

pi->hw.medium_mclk_index = R600_POWER_LEVEL_MEDIUM;

sys/dev/drm/radeon/rv6xx_dpm.c

488

pi->hw.vddc[R600_POWER_LEVEL_MEDIUM] = state->medium.vddc;

sys/dev/drm/radeon/rv6xx_dpm.c

495

pi->hw.backbias[R600_POWER_LEVEL_MEDIUM] =

sys/dev/drm/radeon/rv6xx_dpm.c

502

pi->hw.pcie_gen2[R600_POWER_LEVEL_MEDIUM] =

sys/dev/drm/radeon/rv6xx_dpm.c

515

pi->hw.medium_vddc_index = R600_POWER_LEVEL_MEDIUM;

sys/dev/drm/radeon/rv6xx_dpm.c

593

pi->hw.sclks[R600_POWER_LEVEL_MEDIUM],

sys/dev/drm/radeon/rv6xx_dpm.c

594

R600_POWER_LEVEL_MEDIUM);

sys/dev/drm/radeon/rv6xx_dpm.c

812

STATE1(64 * high_clock / pi->hw.sclks[R600_POWER_LEVEL_MEDIUM]) |

sys/dev/drm/radeon/rv6xx_dpm.c

821

pi->hw.sclks[R600_POWER_LEVEL_MEDIUM])) |

sys/dev/drm/radeon/rv6xx_dpm.c

999

r600_power_level_set_enter_index(rdev, R600_POWER_LEVEL_MEDIUM);