PP_MCLK
return amdgpu_dpm_print_clock_levels(adev, PP_MCLK, buf);
ret = amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
case PP_MCLK:
case PP_MCLK:
case PP_MCLK:
case PP_MCLK:
smu7_force_clock_level(hwmgr, PP_MCLK, 1<<mclk_mask);
case PP_MCLK:
case PP_MCLK:
case PP_MCLK:
case PP_MCLK:
vega10_force_clock_level(hwmgr, PP_MCLK, 1<<mclk_mask);
case PP_MCLK:
vega12_force_clock_level(hwmgr, PP_MCLK, 1 << mclk_mask);
case PP_MCLK:
case PP_MCLK:
case PP_MCLK:
vega20_force_clock_level(hwmgr, PP_MCLK, 1 << mclk_mask);
case PP_MCLK: