sys/dev/drm/amd/powerplay/inc/pp_endian.h

33

#define CONVERT_FROM_HOST_TO_SMC_UL(X) ((X) = PP_HOST_TO_SMC_UL(X))

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1009

table->LinkLevel[i].DownT = PP_HOST_TO_SMC_UL(5);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1010

table->LinkLevel[i].UpT = PP_HOST_TO_SMC_UL(30);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1276

memory_level->MinVddc = PP_HOST_TO_SMC_UL(memory_level->MinVddc * VOLTAGE_SCALE);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1278

memory_level->MinVddci = PP_HOST_TO_SMC_UL(memory_level->MinVddci * VOLTAGE_SCALE);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1279

memory_level->MinMvdd = PP_HOST_TO_SMC_UL(memory_level->MinMvdd * VOLTAGE_SCALE);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1393

table->ACPILevel.MinVddc = PP_HOST_TO_SMC_UL(data->acpi_vddc * VOLTAGE_SCALE);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1395

table->ACPILevel.MinVddc = PP_HOST_TO_SMC_UL(data->min_vddc_in_pptable * VOLTAGE_SCALE);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1451

table->MemoryACPILevel.MinVddci = PP_HOST_TO_SMC_UL(data->acpi_vddci * VOLTAGE_SCALE);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1453

table->MemoryACPILevel.MinVddci = PP_HOST_TO_SMC_UL(data->min_vddci_in_pptable * VOLTAGE_SCALE);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1458

PP_HOST_TO_SMC_UL(voltage_level.Voltage * VOLTAGE_SCALE);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1481

PP_HOST_TO_SMC_UL(dll_cntl);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1483

PP_HOST_TO_SMC_UL(mclk_pwrmgt_cntl);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1485

PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_AD_FUNC_CNTL);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1487

PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_DQ_FUNC_CNTL);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1489

PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1491

PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_1);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1493

PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_2);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1495

PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS1);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1497

PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS2);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1641

arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dramTiming);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1642

arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dramTiming2);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

1754

data->value[i] = PP_HOST_TO_SMC_UL(entry->mc_data[j]);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2792

tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2794

cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2806

tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2809

cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2827

tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2829

cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2841

tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

2844

cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

455

level->MinVddc = PP_HOST_TO_SMC_UL(level->MinVddc * VOLTAGE_SCALE);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

744

dpm_table->BAPM_TEMP_GRADIENT = PP_HOST_TO_SMC_UL(defaults->bapm_temp_gradient);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1405

PP_HOST_TO_SMC_UL(us_mvdd * VOLTAGE_SCALE);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1520

arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dram_timing);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1521

arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2096

table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2582

tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2584

cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2596

tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2599

cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2617

tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2619

cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2631

tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

2634

cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

845

table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

846

table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1324

memory_level->MinVddc = PP_HOST_TO_SMC_UL(memory_level->MinVddc * VOLTAGE_SCALE);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1326

memory_level->MinVddci = PP_HOST_TO_SMC_UL(memory_level->MinVddci * VOLTAGE_SCALE);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1327

memory_level->MinMvdd = PP_HOST_TO_SMC_UL(memory_level->MinMvdd * VOLTAGE_SCALE);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1441

table->ACPILevel.MinVddc = PP_HOST_TO_SMC_UL(data->acpi_vddc * VOLTAGE_SCALE);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1443

table->ACPILevel.MinVddc = PP_HOST_TO_SMC_UL(data->min_vddc_in_pptable * VOLTAGE_SCALE);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1499

table->MemoryACPILevel.MinVddci = PP_HOST_TO_SMC_UL(data->acpi_vddci * VOLTAGE_SCALE);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1501

table->MemoryACPILevel.MinVddci = PP_HOST_TO_SMC_UL(data->min_vddci_in_pptable * VOLTAGE_SCALE);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1506

PP_HOST_TO_SMC_UL(voltage_level.Voltage * VOLTAGE_SCALE);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1529

PP_HOST_TO_SMC_UL(dll_cntl);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1531

PP_HOST_TO_SMC_UL(mclk_pwrmgt_cntl);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1533

PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_AD_FUNC_CNTL);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1535

PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_DQ_FUNC_CNTL);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1537

PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1539

PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_1);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1541

PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_2);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1543

PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS1);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1545

PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS2);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1604

arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dramTiming);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1605

arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dramTiming2);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1722

data->value[i] = PP_HOST_TO_SMC_UL(entry->mc_data[j]);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

1889

dpm_table->BAPM_TEMP_GRADIENT = PP_HOST_TO_SMC_UL(defaults->bapm_temp_gradient);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

782

PP_HOST_TO_SMC_UL(5);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

784

PP_HOST_TO_SMC_UL(30);

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

944

graphic_level->MinVddc = PP_HOST_TO_SMC_UL(graphic_level->MinVddc * VOLTAGE_SCALE);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1265

table->MemoryACPILevel.MinMvdd = PP_HOST_TO_SMC_UL(vol_level.Voltage);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1354

arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dram_timing);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1355

arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1663

table->BTCGB_VDROOP_TABLE[0].a0 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a0);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1664

table->BTCGB_VDROOP_TABLE[0].a1 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a1);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1665

table->BTCGB_VDROOP_TABLE[0].a2 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a2);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1666

table->BTCGB_VDROOP_TABLE[1].a0 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1667

table->BTCGB_VDROOP_TABLE[1].a1 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1668

table->BTCGB_VDROOP_TABLE[1].a2 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1669

table->AVFSGB_VDROOP_TABLE[0].m1 = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_m1);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1671

table->AVFSGB_VDROOP_TABLE[0].b = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_b);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1674

table->AVFSGB_VDROOP_TABLE[1].m1 = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1676

table->AVFSGB_VDROOP_TABLE[1].b = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1680

AVFS_meanNsigma.Aconstant[0] = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant0);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1681

AVFS_meanNsigma.Aconstant[1] = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant1);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1682

AVFS_meanNsigma.Aconstant[2] = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant2);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1944

table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

2435

tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

2437

cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

2449

tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

2452

cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

2470

tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

2472

cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

2484

tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

2487

cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

666

table->MvddLevelCount = (uint32_t) PP_HOST_TO_SMC_UL(count);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

782

table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

783

table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1248

PP_HOST_TO_SMC_UL(voltage_level.Voltage * VOLTAGE_SCALE);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1271

PP_HOST_TO_SMC_UL(dll_cntl);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1273

PP_HOST_TO_SMC_UL(mclk_pwrmgt_cntl);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1275

PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_AD_FUNC_CNTL);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1277

PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_DQ_FUNC_CNTL);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1279

PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1281

PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_1);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1283

PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_2);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1285

PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS1);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1287

PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS2);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1479

arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dramTiming);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1480

arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dramTiming2);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

1853

PP_HOST_TO_SMC_UL(defaults->bapm_temp_gradient);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2100

data->value[i] = PP_HOST_TO_SMC_UL(entry->mc_data[j]);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

2423

table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

3180

tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

3182

cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

3194

tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

3197

cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

3215

tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

3217

cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

3229

tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

3232

cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

524

PP_HOST_TO_SMC_UL(5);

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

526

PP_HOST_TO_SMC_UL(30);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1184

table->MemoryACPILevel.MinMvdd = PP_HOST_TO_SMC_UL(vol_level.Voltage);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1278

arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dram_timing);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1279

arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1280

arb_regs->McArbBurstTime = PP_HOST_TO_SMC_UL(burst_time);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1281

arb_regs->McArbRfshRate = PP_HOST_TO_SMC_UL(rfsh_rate);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1282

arb_regs->McArbMisc3 = PP_HOST_TO_SMC_UL(misc3);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1593

PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a0);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1595

PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a1);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1597

PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a2);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1599

PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1601

PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1603

PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1605

PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_m1);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1609

PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_b);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1613

PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1617

PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1622

PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant0);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1624

PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant1);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1626

PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant2);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

2126

table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

469

table->MvddLevelCount = (uint32_t) PP_HOST_TO_SMC_UL(count);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

586

table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

587

table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);