sys/dev/drm/i915/intel_display.c

1215

pp_reg = PP_CONTROL(0);

sys/dev/drm/i915/intel_display.c

1237

pp_reg = PP_CONTROL(pipe);

sys/dev/drm/i915/intel_display.c

1242

pp_reg = PP_CONTROL(0);

sys/dev/drm/i915/intel_display.c

14260

u32 val = I915_READ(PP_CONTROL(pps_idx));

sys/dev/drm/i915/intel_display.c

14263

I915_WRITE(PP_CONTROL(pps_idx), val);

sys/dev/drm/i915/intel_dp.c

1019

regs->pp_ctrl = PP_CONTROL(pps_idx);

sys/dev/drm/i915/intel_dp.c

1070

pp_ctrl_reg = PP_CONTROL(pipe);

sys/dev/drm/i915/intel_dp.c

897

return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD;

sys/dev/drm/i915/intel_lvds.c

161

pps->powerdown_on_reset = I915_READ(PP_CONTROL(0)) & PANEL_POWER_RESET;

sys/dev/drm/i915/intel_lvds.c

215

val = I915_READ(PP_CONTROL(0));

sys/dev/drm/i915/intel_lvds.c

219

I915_WRITE(PP_CONTROL(0), val);

sys/dev/drm/i915/intel_lvds.c

324

I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) | PANEL_POWER_ON);

sys/dev/drm/i915/intel_lvds.c

340

I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) & ~PANEL_POWER_ON);