sys/dev/drm/amd/powerplay/hwmgr/hardwaremanager.c
368
PP_ASSERT_WITH_CODE((NULL != state), "Invalid Input!", return -EINVAL);
sys/dev/drm/amd/powerplay/hwmgr/hardwaremanager.c
369
PP_ASSERT_WITH_CODE((NULL != pclock_info), "Invalid Input!", return -EINVAL);
sys/dev/drm/amd/powerplay/hwmgr/hardwaremanager.c
373
PP_ASSERT_WITH_CODE((0 == result), "Failed to retrieve minimum clocks.", return result);
sys/dev/drm/amd/powerplay/hwmgr/hardwaremanager.c
384
PP_ASSERT_WITH_CODE((0 == result), "Failed to retrieve maximum clocks.", return result);
sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c
113
PP_ASSERT_WITH_CODE((num_entries <= VBIOS_MC_REGISTER_ARRAY_SIZE),
sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c
1441
PP_ASSERT_WITH_CODE((NULL != voltage_info),
sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c
517
PP_ASSERT_WITH_CODE((NULL != voltage_info),
sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c
537
PP_ASSERT_WITH_CODE((NULL != voltage_info),
sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c
546
PP_ASSERT_WITH_CODE(
sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c
614
PP_ASSERT_WITH_CODE((NULL != table_address),
sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c
632
PP_ASSERT_WITH_CODE((NULL != gpio_lookup_table),
sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c
88
PP_ASSERT_WITH_CODE((*(uint32_t *)reg_data == END_OF_REG_DATA_BLOCK),
sys/dev/drm/amd/powerplay/hwmgr/ppatomfwctrl.c
106
PP_ASSERT_WITH_CODE(voltage_info,
sys/dev/drm/amd/powerplay/hwmgr/ppatomfwctrl.c
118
PP_ASSERT_WITH_CODE(
sys/dev/drm/amd/powerplay/hwmgr/ppatomfwctrl.c
154
PP_ASSERT_WITH_CODE(false,
sys/dev/drm/amd/powerplay/hwmgr/ppatomfwctrl.c
171
PP_ASSERT_WITH_CODE(table_address,
sys/dev/drm/amd/powerplay/hwmgr/ppatomfwctrl.c
217
PP_ASSERT_WITH_CODE(gpio_lookup_table,
sys/dev/drm/amd/powerplay/hwmgr/ppatomfwctrl.c
64
PP_ASSERT_WITH_CODE(table_address,
sys/dev/drm/amd/powerplay/hwmgr/ppatomfwctrl.c
85
PP_ASSERT_WITH_CODE(voltage_info,
sys/dev/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
1045
PP_ASSERT_WITH_CODE((ATOM_Tonga_TABLE_REVISION_TONGA <=
sys/dev/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
1048
PP_ASSERT_WITH_CODE((0 != powerplay_table->usStateArrayOffset),
sys/dev/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
1050
PP_ASSERT_WITH_CODE((0 < powerplay_table->sHeader.usStructureSize),
sys/dev/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
1052
PP_ASSERT_WITH_CODE((0 < state_arrays->ucNumEntries),
sys/dev/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
1065
PP_ASSERT_WITH_CODE((NULL != hwmgr->pptable),
sys/dev/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
1072
PP_ASSERT_WITH_CODE((NULL != powerplay_table),
sys/dev/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
1077
PP_ASSERT_WITH_CODE((result == 0),
sys/dev/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
1083
PP_ASSERT_WITH_CODE((result == 0),
sys/dev/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
1088
PP_ASSERT_WITH_CODE((result == 0),
sys/dev/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
1093
PP_ASSERT_WITH_CODE((result == 0),
sys/dev/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
1098
PP_ASSERT_WITH_CODE((result == 0),
sys/dev/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
1103
PP_ASSERT_WITH_CODE((result == 0),
sys/dev/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
1166
PP_ASSERT_WITH_CODE((NULL != pp_table),
sys/dev/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
1168
PP_ASSERT_WITH_CODE((pp_table->sHeader.ucTableFormatRevision >=
sys/dev/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
1242
PP_ASSERT_WITH_CODE((i < vce_state_table->ucNumEntries),
sys/dev/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
1298
PP_ASSERT_WITH_CODE((NULL != pp_table), "Missing PowerPlay Table!", return -1;);
sys/dev/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
1306
PP_ASSERT_WITH_CODE((0 < pp_table->usStateArrayOffset),
sys/dev/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
1308
PP_ASSERT_WITH_CODE((0 < state_arrays->ucNumEntries),
sys/dev/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
1310
PP_ASSERT_WITH_CODE((entry_index <= state_arrays->ucNumEntries),
sys/dev/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
165
PP_ASSERT_WITH_CODE((0 != vddc_lookup_pp_tables->ucNumEntries),
sys/dev/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
325
PP_ASSERT_WITH_CODE((0 != clk_volt_pp_table->count),
sys/dev/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
355
PP_ASSERT_WITH_CODE((0 != limitable->ucNumEntries), "Invalid PowerPlay Table!", return -1);
sys/dev/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
378
PP_ASSERT_WITH_CODE((0 != mclk_dep_table->ucNumEntries),
sys/dev/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
425
PP_ASSERT_WITH_CODE((0 != tonga_table->ucNumEntries),
sys/dev/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
457
PP_ASSERT_WITH_CODE((0 != polaris_table->ucNumEntries),
sys/dev/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
507
PP_ASSERT_WITH_CODE((atom_pcie_table->ucNumEntries != 0),
sys/dev/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
546
PP_ASSERT_WITH_CODE((atom_pcie_table->ucNumEntries != 0),
sys/dev/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
57
PP_ASSERT_WITH_CODE((~powerplay_caps & ____RETIRE16____),
sys/dev/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
59
PP_ASSERT_WITH_CODE((~powerplay_caps & ____RETIRE64____),
sys/dev/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
61
PP_ASSERT_WITH_CODE((~powerplay_caps & ____RETIRE512____),
sys/dev/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
63
PP_ASSERT_WITH_CODE((~powerplay_caps & ____RETIRE1024____),
sys/dev/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
65
PP_ASSERT_WITH_CODE((~powerplay_caps & ____RETIRE2048____),
sys/dev/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
698
PP_ASSERT_WITH_CODE((0 != mm_dependency_table->ucNumEntries),
sys/dev/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
747
PP_ASSERT_WITH_CODE(false,
sys/dev/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
894
PP_ASSERT_WITH_CODE((0 != powerplay_table->usThermalControllerOffset),
sys/dev/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
926
PP_ASSERT_WITH_CODE((0 != powerplay_table->usFanTableOffset),
sys/dev/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
928
PP_ASSERT_WITH_CODE((0 < fan_table->ucRevId),
sys/dev/drm/amd/powerplay/hwmgr/processpptables.c
1607
PP_ASSERT_WITH_CODE((result == 0),
sys/dev/drm/amd/powerplay/hwmgr/processpptables.c
1613
PP_ASSERT_WITH_CODE((result == 0),
sys/dev/drm/amd/powerplay/hwmgr/processpptables.c
1618
PP_ASSERT_WITH_CODE((result == 0),
sys/dev/drm/amd/powerplay/hwmgr/processpptables.c
1623
PP_ASSERT_WITH_CODE((result == 0),
sys/dev/drm/amd/powerplay/hwmgr/processpptables.c
1629
PP_ASSERT_WITH_CODE((result == 0),
sys/dev/drm/amd/powerplay/hwmgr/processpptables.c
1634
PP_ASSERT_WITH_CODE((result == 0),
sys/dev/drm/amd/powerplay/hwmgr/processpptables.c
1639
PP_ASSERT_WITH_CODE((result == 0),
sys/dev/drm/amd/powerplay/hwmgr/processpptables.c
856
PP_ASSERT_WITH_CODE(NULL != powerplay_tab,
sys/dev/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
208
PP_ASSERT_WITH_CODE(!smu10_display_clock_voltage_request(hwmgr, &clock_req),
sys/dev/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
429
PP_ASSERT_WITH_CODE((0 == result),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
1016
PP_ASSERT_WITH_CODE(false,
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
1022
PP_ASSERT_WITH_CODE(false,
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
1037
PP_ASSERT_WITH_CODE(false,
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
1088
PP_ASSERT_WITH_CODE(
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
1099
PP_ASSERT_WITH_CODE(
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
113
PP_ASSERT_WITH_CODE((PhwVIslands_Magic == hw_ps->magic),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
1170
PP_ASSERT_WITH_CODE(
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
1179
PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(hwmgr,
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
1194
PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
1202
PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
1224
PP_ASSERT_WITH_CODE(
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
123
PP_ASSERT_WITH_CODE((PhwVIslands_Magic == hw_ps->magic),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
1233
PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
1331
PP_ASSERT_WITH_CODE(tmp_result == 0,
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
1336
PP_ASSERT_WITH_CODE((0 == tmp_result),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
1353
PP_ASSERT_WITH_CODE((0 == tmp_result),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
1358
PP_ASSERT_WITH_CODE((0 == tmp_result),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
1362
PP_ASSERT_WITH_CODE((0 == tmp_result),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
1366
PP_ASSERT_WITH_CODE((0 == tmp_result),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
1371
PP_ASSERT_WITH_CODE((0 == tmp_result),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
1377
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
1381
PP_ASSERT_WITH_CODE((0 == tmp_result),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
1385
PP_ASSERT_WITH_CODE((0 == tmp_result),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
1391
PP_ASSERT_WITH_CODE((0 == tmp_result),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
1395
PP_ASSERT_WITH_CODE((0 == tmp_result),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
1399
PP_ASSERT_WITH_CODE((0 == tmp_result),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
1403
PP_ASSERT_WITH_CODE((0 == tmp_result),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
1407
PP_ASSERT_WITH_CODE((tmp_result == 0),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
1411
PP_ASSERT_WITH_CODE((0 == tmp_result),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
1415
PP_ASSERT_WITH_CODE((0 == tmp_result),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
1419
PP_ASSERT_WITH_CODE((0 == tmp_result),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
1423
PP_ASSERT_WITH_CODE((0 == tmp_result),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
1427
PP_ASSERT_WITH_CODE((0 == tmp_result),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
1431
PP_ASSERT_WITH_CODE((0 == tmp_result),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
1445
PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
1452
PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
1491
PP_ASSERT_WITH_CODE((tmp_result == 0),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
1495
PP_ASSERT_WITH_CODE((tmp_result == 0),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
1499
PP_ASSERT_WITH_CODE((tmp_result == 0),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
1508
PP_ASSERT_WITH_CODE((tmp_result == 0),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
1512
PP_ASSERT_WITH_CODE((tmp_result == 0),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
1516
PP_ASSERT_WITH_CODE((tmp_result == 0),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
1520
PP_ASSERT_WITH_CODE((tmp_result == 0),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
1524
PP_ASSERT_WITH_CODE((tmp_result == 0),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
1528
PP_ASSERT_WITH_CODE((tmp_result == 0),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
1532
PP_ASSERT_WITH_CODE((tmp_result == 0),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
1536
PP_ASSERT_WITH_CODE((tmp_result == 0),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
164
PP_ASSERT_WITH_CODE((7 >= link_width),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
1729
PP_ASSERT_WITH_CODE((vddgfx < 2000 && vddgfx != 0), "Invalid VDDGFX value!", return -EINVAL);
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
1894
PP_ASSERT_WITH_CODE((NULL != look_up_table),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
1896
PP_ASSERT_WITH_CODE((0 != look_up_table->count),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
1900
PP_ASSERT_WITH_CODE((i >= look_up_table->count),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
2000
PP_ASSERT_WITH_CODE(0 != lookup_table->count,
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
2080
PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL,
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
2083
PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
2087
PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL,
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
2090
PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
225
PP_ASSERT_WITH_CODE((NULL != voltage_table),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
2462
PP_ASSERT_WITH_CODE(allowed_sclk_vddc_table != NULL,
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
2465
PP_ASSERT_WITH_CODE(allowed_sclk_vddc_table->count >= 1,
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
2469
PP_ASSERT_WITH_CODE(allowed_mclk_vddc_table != NULL,
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
2472
PP_ASSERT_WITH_CODE(allowed_mclk_vddc_table->count >= 1,
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
260
PP_ASSERT_WITH_CODE((0 == result),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
271
PP_ASSERT_WITH_CODE((0 == result),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
280
PP_ASSERT_WITH_CODE((0 == result),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
290
PP_ASSERT_WITH_CODE((0 == result),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
2903
PP_ASSERT_WITH_CODE(smu7_ps->performance_level_count == 2,
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
299
PP_ASSERT_WITH_CODE((0 == result),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
308
PP_ASSERT_WITH_CODE((0 == result),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
3167
PP_ASSERT_WITH_CODE(
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
3172
PP_ASSERT_WITH_CODE(
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
319
PP_ASSERT_WITH_CODE((0 == result),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
324
PP_ASSERT_WITH_CODE(
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
331
PP_ASSERT_WITH_CODE(
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
3331
PP_ASSERT_WITH_CODE(
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
3336
PP_ASSERT_WITH_CODE(
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
338
PP_ASSERT_WITH_CODE(
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
345
PP_ASSERT_WITH_CODE(
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
3708
PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
3711
PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr,
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
3720
PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
3723
PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr,
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
3763
PP_ASSERT_WITH_CODE((0 == result),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
3772
PP_ASSERT_WITH_CODE((0 == result),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
3804
PP_ASSERT_WITH_CODE((smu7_ps->performance_level_count >= 1),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
3859
PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
3862
PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr,
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
3871
PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
3874
PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr,
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
3942
PP_ASSERT_WITH_CODE((0 == tmp_result),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
3950
PP_ASSERT_WITH_CODE((0 == tmp_result),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
3956
PP_ASSERT_WITH_CODE((0 == tmp_result),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
3960
PP_ASSERT_WITH_CODE((0 == tmp_result),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
3965
PP_ASSERT_WITH_CODE((0 == tmp_result),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
3970
PP_ASSERT_WITH_CODE((0 == tmp_result),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
3975
PP_ASSERT_WITH_CODE((0 == tmp_result),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
3980
PP_ASSERT_WITH_CODE((0 == tmp_result),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
3985
PP_ASSERT_WITH_CODE((0 == tmp_result),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
3990
PP_ASSERT_WITH_CODE((0 == tmp_result),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
3998
PP_ASSERT_WITH_CODE((0 == tmp_result),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
4335
PP_ASSERT_WITH_CODE((0 == tmp_result),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
4339
PP_ASSERT_WITH_CODE((0 == tmp_result),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
4343
PP_ASSERT_WITH_CODE((0 == tmp_result),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
4347
PP_ASSERT_WITH_CODE((0 == tmp_result),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
4351
PP_ASSERT_WITH_CODE((0 == tmp_result),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
4355
PP_ASSERT_WITH_CODE((0 == tmp_result),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
4823
PP_ASSERT_WITH_CODE(input, "NULL user input for clock and voltage",
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
4834
PP_ASSERT_WITH_CODE((podn_dpm_table_in_backend && podn_vdd_dep_in_backend),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
4841
PP_ASSERT_WITH_CODE((podn_dpm_table_in_backend && podn_vdd_dep_in_backend),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
5051
PP_ASSERT_WITH_CODE((0 == result),
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
5125
PP_ASSERT_WITH_CODE((clock >= min), "Engine clock can't satisfy stutter requirement!", return 0);
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
535
PP_ASSERT_WITH_CODE((data->use_pcie_performance_levels ||
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
677
PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table != NULL,
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
679
PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table->count >= 1,
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
682
PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table != NULL,
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
684
PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table->count >= 1,
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
701
PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table != NULL,
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
768
PP_ASSERT_WITH_CODE(dep_sclk_table != NULL,
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
771
PP_ASSERT_WITH_CODE(dep_sclk_table->count >= 1,
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
775
PP_ASSERT_WITH_CODE(dep_mclk_table != NULL,
sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
778
PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1,
sys/dev/drm/amd/powerplay/hwmgr/smu7_powertune.c
1000
PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", goto error);
sys/dev/drm/amd/powerplay/hwmgr/smu7_powertune.c
1002
PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", goto error);
sys/dev/drm/amd/powerplay/hwmgr/smu7_powertune.c
1008
PP_ASSERT_WITH_CODE((result == 0), "EnableDiDt failed.", goto error);
sys/dev/drm/amd/powerplay/hwmgr/smu7_powertune.c
1013
PP_ASSERT_WITH_CODE((0 == result),
sys/dev/drm/amd/powerplay/hwmgr/smu7_powertune.c
1040
PP_ASSERT_WITH_CODE((result == 0),
sys/dev/drm/amd/powerplay/hwmgr/smu7_powertune.c
1046
PP_ASSERT_WITH_CODE((0 == result),
sys/dev/drm/amd/powerplay/hwmgr/smu7_powertune.c
1067
PP_ASSERT_WITH_CODE((0 == smc_result),
sys/dev/drm/amd/powerplay/hwmgr/smu7_powertune.c
1083
PP_ASSERT_WITH_CODE((smc_result == 0),
sys/dev/drm/amd/powerplay/hwmgr/smu7_powertune.c
1128
PP_ASSERT_WITH_CODE((0 == smc_result),
sys/dev/drm/amd/powerplay/hwmgr/smu7_powertune.c
1138
PP_ASSERT_WITH_CODE((0 == smc_result),
sys/dev/drm/amd/powerplay/hwmgr/smu7_powertune.c
1167
PP_ASSERT_WITH_CODE((smc_result == 0),
sys/dev/drm/amd/powerplay/hwmgr/smu7_powertune.c
1176
PP_ASSERT_WITH_CODE((smc_result == 0),
sys/dev/drm/amd/powerplay/hwmgr/smu7_powertune.c
1185
PP_ASSERT_WITH_CODE((smc_result == 0),
sys/dev/drm/amd/powerplay/hwmgr/smu7_powertune.c
902
PP_ASSERT_WITH_CODE((config_regs != NULL), "Invalid config register table.", return -EINVAL);
sys/dev/drm/amd/powerplay/hwmgr/smu7_powertune.c
982
PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", goto error);
sys/dev/drm/amd/powerplay/hwmgr/smu7_powertune.c
984
PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", goto error);
sys/dev/drm/amd/powerplay/hwmgr/smu7_powertune.c
987
PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", goto error);
sys/dev/drm/amd/powerplay/hwmgr/smu7_powertune.c
992
PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", goto error);
sys/dev/drm/amd/powerplay/hwmgr/smu7_powertune.c
995
PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", goto error);
sys/dev/drm/amd/powerplay/hwmgr/smu7_powertune.c
997
PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", goto error);
sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
459
PP_ASSERT_WITH_CODE((0 == ret && NULL != table),
sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
465
PP_ASSERT_WITH_CODE((vddc_table->count <= SMU8_MAX_HARDWARE_POWERLEVELS),
sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
467
PP_ASSERT_WITH_CODE((vdd_gfx_table->count <= SMU8_MAX_HARDWARE_POWERLEVELS),
sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
469
PP_ASSERT_WITH_CODE((acp_table->count <= SMU8_MAX_HARDWARE_POWERLEVELS),
sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
471
PP_ASSERT_WITH_CODE((uvd_table->count <= SMU8_MAX_HARDWARE_POWERLEVELS),
sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
473
PP_ASSERT_WITH_CODE((vce_table->count <= SMU8_MAX_HARDWARE_POWERLEVELS),
sys/dev/drm/amd/powerplay/hwmgr/smu_helper.c
207
PP_ASSERT_WITH_CODE((NULL != vol_table),
sys/dev/drm/amd/powerplay/hwmgr/smu_helper.c
250
PP_ASSERT_WITH_CODE((0 != dep_table->count),
sys/dev/drm/amd/powerplay/hwmgr/smu_helper.c
253
PP_ASSERT_WITH_CODE((NULL != vol_table),
sys/dev/drm/amd/powerplay/hwmgr/smu_helper.c
266
PP_ASSERT_WITH_CODE((0 == result),
sys/dev/drm/amd/powerplay/hwmgr/smu_helper.c
278
PP_ASSERT_WITH_CODE((0 != dep_table->count),
sys/dev/drm/amd/powerplay/hwmgr/smu_helper.c
281
PP_ASSERT_WITH_CODE((NULL != vol_table),
sys/dev/drm/amd/powerplay/hwmgr/smu_helper.c
294
PP_ASSERT_WITH_CODE((0 == result),
sys/dev/drm/amd/powerplay/hwmgr/smu_helper.c
305
PP_ASSERT_WITH_CODE((0 != lookup_table->count),
sys/dev/drm/amd/powerplay/hwmgr/smu_helper.c
308
PP_ASSERT_WITH_CODE((NULL != vol_table),
sys/dev/drm/amd/powerplay/hwmgr/smu_helper.c
391
PP_ASSERT_WITH_CODE((NULL != lookup_table),
sys/dev/drm/amd/powerplay/hwmgr/smu_helper.c
393
PP_ASSERT_WITH_CODE((0 != count),
sys/dev/drm/amd/powerplay/hwmgr/smu_helper.c
411
PP_ASSERT_WITH_CODE((NULL != voltage_table),
sys/dev/drm/amd/powerplay/hwmgr/smu_helper.c
413
PP_ASSERT_WITH_CODE((0 != count),
sys/dev/drm/amd/powerplay/hwmgr/smu_helper.c
465
PP_ASSERT_WITH_CODE(lookup_table->count != 0, "Lookup table is empty", return -EINVAL);
sys/dev/drm/amd/powerplay/hwmgr/smu_helper.c
680
PP_ASSERT_WITH_CODE((0 != allowed_dep_table->count),
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
1032
PP_ASSERT_WITH_CODE(dep_table->count,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
1045
PP_ASSERT_WITH_CODE(!vega10_trim_voltage_table(hwmgr,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
1059
PP_ASSERT_WITH_CODE(dep_table->count,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
1072
PP_ASSERT_WITH_CODE(!vega10_trim_voltage_table(hwmgr, vol_table),
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
1085
PP_ASSERT_WITH_CODE(dep_table->count,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
1142
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
1151
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
1161
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
1166
PP_ASSERT_WITH_CODE(data->vddc_voltage_table.count <= 16,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
1171
PP_ASSERT_WITH_CODE(data->vddci_voltage_table.count <= 16,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
1176
PP_ASSERT_WITH_CODE(data->mvdd_voltage_table.count <= 16,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
1228
PP_ASSERT_WITH_CODE(bios_pcie_table->count,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
1292
PP_ASSERT_WITH_CODE(dep_soc_table,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
1295
PP_ASSERT_WITH_CODE(dep_soc_table->count >= 1,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
1299
PP_ASSERT_WITH_CODE(dep_gfx_table,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
1302
PP_ASSERT_WITH_CODE(dep_gfx_table->count >= 1,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
1306
PP_ASSERT_WITH_CODE(dep_mclk_table,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
1309
PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
1459
PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
1536
PP_ASSERT_WITH_CODE(dep_on_sclk,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
1547
PP_ASSERT_WITH_CODE(dep_on_sclk->count > i,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
1552
PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
1608
PP_ASSERT_WITH_CODE(dep_on_soc->count > i,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
1612
PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
1737
PP_ASSERT_WITH_CODE(dep_on_mclk,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
1748
PP_ASSERT_WITH_CODE(dep_on_mclk->count > i,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
1753
PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
1765
PP_ASSERT_WITH_CODE(current_memclk_level->Did >= 1,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
1850
PP_ASSERT_WITH_CODE(dep_table->count <= NUM_DSPCLK_LEVELS,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
1881
PP_ASSERT_WITH_CODE(!vega10_populate_single_display_type(hwmgr, i),
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
1900
PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
1952
PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
1968
PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
2346
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
2353
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
2412
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
2473
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
2513
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
2519
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
2524
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
2529
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
2536
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
2541
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
2546
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
2552
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
2586
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
2591
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
2608
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
2612
PP_ASSERT_WITH_CODE(!result, "Attempt to enable AVFS feature Failed!",
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
2627
PP_ASSERT_WITH_CODE(
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
2647
PP_ASSERT_WITH_CODE(
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
2665
PP_ASSERT_WITH_CODE(
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
2674
PP_ASSERT_WITH_CODE(
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
2692
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
2707
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
2722
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
2730
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
2738
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
2746
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
2761
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
2769
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
2777
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
2785
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
2802
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
2859
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
2873
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
2891
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
2912
PP_ASSERT_WITH_CODE(!tmp_result,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
2917
PP_ASSERT_WITH_CODE(!tmp_result,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
2923
PP_ASSERT_WITH_CODE(!tmp_result,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
2929
PP_ASSERT_WITH_CODE(!tmp_result,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
2934
PP_ASSERT_WITH_CODE(!tmp_result,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
2939
PP_ASSERT_WITH_CODE(!tmp_result,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
2948
PP_ASSERT_WITH_CODE(!tmp_result,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
2953
PP_ASSERT_WITH_CODE(!tmp_result,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
2958
PP_ASSERT_WITH_CODE(!tmp_result,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
3028
PP_ASSERT_WITH_CODE(
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
3034
PP_ASSERT_WITH_CODE(
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
3154
PP_ASSERT_WITH_CODE(
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
3323
PP_ASSERT_WITH_CODE((0 == result),
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
3331
PP_ASSERT_WITH_CODE((0 == result),
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
3382
PP_ASSERT_WITH_CODE((vega10_ps->performance_level_count >= 1),
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
3535
PP_ASSERT_WITH_CODE(!vega10_trim_dpm_states(hwmgr, vega10_ps),
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
3548
PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
3551
PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
3569
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
3610
PP_ASSERT_WITH_CODE(!tmp_result,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
3615
PP_ASSERT_WITH_CODE(!tmp_result,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
3620
PP_ASSERT_WITH_CODE(!tmp_result,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
3625
PP_ASSERT_WITH_CODE(!tmp_result,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
3630
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
3899
PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
3903
PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
3921
PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
3925
PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
3946
PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
3950
PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
4013
PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
4017
PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
4026
PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
4030
PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
4371
PP_ASSERT_WITH_CODE(result, "Failed to update WMTABLE!", return EINVAL);
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
4389
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
4484
PP_ASSERT_WITH_CODE((tmp_result == 0),
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
4488
PP_ASSERT_WITH_CODE((tmp_result == 0),
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
4492
PP_ASSERT_WITH_CODE((tmp_result == 0),
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
4496
PP_ASSERT_WITH_CODE((tmp_result == 0),
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
4500
PP_ASSERT_WITH_CODE((tmp_result == 0),
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
4504
PP_ASSERT_WITH_CODE((tmp_result == 0),
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
4508
PP_ASSERT_WITH_CODE((tmp_result == 0),
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
4521
PP_ASSERT_WITH_CODE((0 == result),
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
4856
PP_ASSERT_WITH_CODE(input, "NULL user input for clock and voltage",
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
501
PP_ASSERT_WITH_CODE(lookup_table->count != 0,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
512
PP_ASSERT_WITH_CODE(entry_id < table_info->vdd_dep_on_socclk->count,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
556
PP_ASSERT_WITH_CODE(!atomctrl_get_voltage_evv_on_sclk_ai(hwmgr,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
563
PP_ASSERT_WITH_CODE((vddc < 2000 && vddc != 0),
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
694
PP_ASSERT_WITH_CODE(lookup_table && lookup_table->count,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
754
PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
756
PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
759
PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
761
PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
80
PP_ASSERT_WITH_CODE((PhwVega10_Magic == hw_ps->magic),
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
835
PP_ASSERT_WITH_CODE(false,
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
868
PP_ASSERT_WITH_CODE(!vega10_get_evv_voltages(hwmgr),
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
911
PP_ASSERT_WITH_CODE(data->mem_channels < ARRAY_SIZE(channel_number),
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
92
PP_ASSERT_WITH_CODE((PhwVega10_Magic == hw_ps->magic),
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
961
PP_ASSERT_WITH_CODE(!vega10_init_sclk_threshold(hwmgr),
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
965
PP_ASSERT_WITH_CODE(!vega10_setup_dpm_led_config(hwmgr),
sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
990
PP_ASSERT_WITH_CODE(vol_table,
sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c
1190
PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDtConfig] Pre DIDT disable clock gating failed!", return result);
sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c
1207
PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 0 Failed!", return result);
sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c
1211
PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 2 Failed!", return result);
sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c
1215
PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 3 Failed!", return result);
sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c
1221
PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 5 Failed!", return result);
sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c
1225
PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 6 Failed!", return result);
sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c
1234
PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDtConfig] Attempt to Enable DiDt feature Failed!", return result);
sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c
1254
PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] Attempt to disable DiDt Mode 0 Failed!", return result);
sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c
1258
PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] Attempt to disable DiDt Mode 2 Failed!", return result);
sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c
1262
PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] Attempt to disable DiDt Mode 3 Failed!", return result);
sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c
1268
PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] Attempt to disable DiDt Mode 5 Failed!", return result);
sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c
1272
PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] Attempt to disable DiDt Mode 6 Failed!", return result);
sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c
1281
PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDtConfig] Attempt to Disable DiDt feature Failed!", return result);
sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c
1352
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c
1358
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c
1364
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c
1378
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c
1384
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
sys/dev/drm/amd/powerplay/hwmgr/vega10_powertune.c
807
PP_ASSERT_WITH_CODE((config_regs != NULL), "[vega10_program_didt_config_registers] Invalid config register table!", return -EINVAL);
sys/dev/drm/amd/powerplay/hwmgr/vega10_processpptables.c
1023
PP_ASSERT_WITH_CODE((vddc_lookup_pp_tables->ucNumEntries != 0),
sys/dev/drm/amd/powerplay/hwmgr/vega10_processpptables.c
1141
PP_ASSERT_WITH_CODE((hwmgr->pptable != NULL),
sys/dev/drm/amd/powerplay/hwmgr/vega10_processpptables.c
1146
PP_ASSERT_WITH_CODE((powerplay_table != NULL),
sys/dev/drm/amd/powerplay/hwmgr/vega10_processpptables.c
1151
PP_ASSERT_WITH_CODE((result == 0),
sys/dev/drm/amd/powerplay/hwmgr/vega10_processpptables.c
1157
PP_ASSERT_WITH_CODE((result == 0),
sys/dev/drm/amd/powerplay/hwmgr/vega10_processpptables.c
1162
PP_ASSERT_WITH_CODE((result == 0),
sys/dev/drm/amd/powerplay/hwmgr/vega10_processpptables.c
1167
PP_ASSERT_WITH_CODE((result == 0),
sys/dev/drm/amd/powerplay/hwmgr/vega10_processpptables.c
1172
PP_ASSERT_WITH_CODE((result == 0),
sys/dev/drm/amd/powerplay/hwmgr/vega10_processpptables.c
1177
PP_ASSERT_WITH_CODE((result == 0),
sys/dev/drm/amd/powerplay/hwmgr/vega10_processpptables.c
1240
PP_ASSERT_WITH_CODE((pp_table != NULL),
sys/dev/drm/amd/powerplay/hwmgr/vega10_processpptables.c
1242
PP_ASSERT_WITH_CODE((pp_table->sHeader.format_revision >=
sys/dev/drm/amd/powerplay/hwmgr/vega10_processpptables.c
1292
PP_ASSERT_WITH_CODE(pp_table, "Missing PowerPlay Table!",
sys/dev/drm/amd/powerplay/hwmgr/vega10_processpptables.c
1302
PP_ASSERT_WITH_CODE(pp_table->usStateArrayOffset > 0,
sys/dev/drm/amd/powerplay/hwmgr/vega10_processpptables.c
1305
PP_ASSERT_WITH_CODE(state_arrays->ucNumEntries > 0,
sys/dev/drm/amd/powerplay/hwmgr/vega10_processpptables.c
1308
PP_ASSERT_WITH_CODE((entry_index <= state_arrays->ucNumEntries),
sys/dev/drm/amd/powerplay/hwmgr/vega10_processpptables.c
131
PP_ASSERT_WITH_CODE((powerplay_table->usThermalControllerOffset != 0),
sys/dev/drm/amd/powerplay/hwmgr/vega10_processpptables.c
169
PP_ASSERT_WITH_CODE((fan_table_v1->ucRevId >= 8),
sys/dev/drm/amd/powerplay/hwmgr/vega10_processpptables.c
302
PP_ASSERT_WITH_CODE((mm_dependency_table->ucNumEntries != 0),
sys/dev/drm/amd/powerplay/hwmgr/vega10_processpptables.c
528
PP_ASSERT_WITH_CODE(clk_dep_table->ucNumEntries,
sys/dev/drm/amd/powerplay/hwmgr/vega10_processpptables.c
562
PP_ASSERT_WITH_CODE(mclk_dep_table->ucNumEntries,
sys/dev/drm/amd/powerplay/hwmgr/vega10_processpptables.c
603
PP_ASSERT_WITH_CODE((clk_dep_table->ucNumEntries != 0),
sys/dev/drm/amd/powerplay/hwmgr/vega10_processpptables.c
649
PP_ASSERT_WITH_CODE(false,
sys/dev/drm/amd/powerplay/hwmgr/vega10_processpptables.c
669
PP_ASSERT_WITH_CODE((clk_dep_table->ucNumEntries != 0),
sys/dev/drm/amd/powerplay/hwmgr/vega10_processpptables.c
709
PP_ASSERT_WITH_CODE((clk_dep_table->ucNumEntries != 0),
sys/dev/drm/amd/powerplay/hwmgr/vega10_processpptables.c
75
PP_ASSERT_WITH_CODE((powerplay_table->sHeader.format_revision >=
sys/dev/drm/amd/powerplay/hwmgr/vega10_processpptables.c
768
PP_ASSERT_WITH_CODE(atom_pcie_table->ucNumEntries,
sys/dev/drm/amd/powerplay/hwmgr/vega10_processpptables.c
78
PP_ASSERT_WITH_CODE(powerplay_table->usStateArrayOffset,
sys/dev/drm/amd/powerplay/hwmgr/vega10_processpptables.c
80
PP_ASSERT_WITH_CODE(powerplay_table->sHeader.structuresize > 0,
sys/dev/drm/amd/powerplay/hwmgr/vega10_processpptables.c
810
PP_ASSERT_WITH_CODE(limit_table->ucNumEntries,
sys/dev/drm/amd/powerplay/hwmgr/vega10_processpptables.c
82
PP_ASSERT_WITH_CODE(state_arrays->ucNumEntries > 0,
sys/dev/drm/amd/powerplay/hwmgr/vega10_processpptables.c
832
PP_ASSERT_WITH_CODE(clk_volt_pp_table->count,
sys/dev/drm/amd/powerplay/hwmgr/vega10_thermal.c
188
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(
sys/dev/drm/amd/powerplay/hwmgr/vega10_thermal.c
205
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(
sys/dev/drm/amd/powerplay/hwmgr/vega10_thermal.c
222
PP_ASSERT_WITH_CODE(!vega10_enable_fan_control_feature(hwmgr),
sys/dev/drm/amd/powerplay/hwmgr/vega10_thermal.c
238
PP_ASSERT_WITH_CODE(!vega10_disable_fan_control_feature(hwmgr),
sys/dev/drm/amd/powerplay/hwmgr/vega10_thermal.c
435
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
sys/dev/drm/amd/powerplay/hwmgr/vega10_thermal.c
466
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
1014
PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
1023
PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
1030
PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
1040
PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
1048
PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
1058
PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
1068
PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
1088
PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
1098
PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
1108
PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
1115
PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
1125
PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
1135
PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
1151
PP_ASSERT_WITH_CODE(!vega12_enable_smc_features(hwmgr,
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
1172
PP_ASSERT_WITH_CODE(
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
1177
PP_ASSERT_WITH_CODE(
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
1195
PP_ASSERT_WITH_CODE(
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
1200
PP_ASSERT_WITH_CODE(
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
1213
PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
1231
PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr,
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
1248
PP_ASSERT_WITH_CODE(
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
1413
PP_ASSERT_WITH_CODE(
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
1446
PP_ASSERT_WITH_CODE(!vega12_upload_dpm_min_level(hwmgr),
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
1450
PP_ASSERT_WITH_CODE(!vega12_upload_dpm_max_level(hwmgr),
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
1475
PP_ASSERT_WITH_CODE(!vega12_upload_dpm_min_level(hwmgr),
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
1479
PP_ASSERT_WITH_CODE(!vega12_upload_dpm_max_level(hwmgr),
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
1489
PP_ASSERT_WITH_CODE(!vega12_upload_dpm_min_level(hwmgr),
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
1493
PP_ASSERT_WITH_CODE(!vega12_upload_dpm_max_level(hwmgr),
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
1816
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
1821
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
1836
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
1841
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
1865
PP_ASSERT_WITH_CODE(
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
1870
PP_ASSERT_WITH_CODE(
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
1881
PP_ASSERT_WITH_CODE(
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
1886
PP_ASSERT_WITH_CODE(
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
2072
PP_ASSERT_WITH_CODE(dpm_table->count > 0,
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
2075
PP_ASSERT_WITH_CODE(dpm_table->count <= NUM_UCLK_DPM_LEVELS,
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
2080
PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr,
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
2114
PP_ASSERT_WITH_CODE(result, "Failed to update WMTABLE!", return EINVAL);
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
2134
PP_ASSERT_WITH_CODE(!vega12_enable_smc_features(hwmgr,
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
2189
PP_ASSERT_WITH_CODE((tmp_result == 0),
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
2201
PP_ASSERT_WITH_CODE((0 == result),
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
446
PP_ASSERT_WITH_CODE(!vega12_init_sclk_threshold(hwmgr),
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
476
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
481
PP_ASSERT_WITH_CODE(*num_of_levels > 0,
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
497
PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr,
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
514
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
522
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
554
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
567
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
580
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
593
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
606
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
619
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
632
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
645
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
656
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
667
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
750
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
769
PP_ASSERT_WITH_CODE(
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
774
PP_ASSERT_WITH_CODE(
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
805
PP_ASSERT_WITH_CODE(
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
831
PP_ASSERT_WITH_CODE(
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
879
PP_ASSERT_WITH_CODE(
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
886
PP_ASSERT_WITH_CODE(
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
893
PP_ASSERT_WITH_CODE(
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
909
PP_ASSERT_WITH_CODE(!vega12_get_all_clock_ranges_helper(hwmgr,
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
925
PP_ASSERT_WITH_CODE(result == 0,
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
930
PP_ASSERT_WITH_CODE(!tmp_result,
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
935
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
940
PP_ASSERT_WITH_CODE(!tmp_result,
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
945
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
950
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
955
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
989
PP_ASSERT_WITH_CODE(table->count <= MAX_REGULAR_DPM_NUMBER,
sys/dev/drm/amd/powerplay/hwmgr/vega12_processpptables.c
106
PP_ASSERT_WITH_CODE(
sys/dev/drm/amd/powerplay/hwmgr/vega12_processpptables.c
273
PP_ASSERT_WITH_CODE((hwmgr->pptable != NULL),
sys/dev/drm/amd/powerplay/hwmgr/vega12_processpptables.c
277
PP_ASSERT_WITH_CODE((powerplay_table != NULL),
sys/dev/drm/amd/powerplay/hwmgr/vega12_processpptables.c
281
PP_ASSERT_WITH_CODE((result == 0),
sys/dev/drm/amd/powerplay/hwmgr/vega12_processpptables.c
286
PP_ASSERT_WITH_CODE((result == 0),
sys/dev/drm/amd/powerplay/hwmgr/vega12_processpptables.c
290
PP_ASSERT_WITH_CODE((result == 0),
sys/dev/drm/amd/powerplay/hwmgr/vega12_processpptables.c
368
PP_ASSERT_WITH_CODE(pp_table, "Missing PowerPlay Table!",
sys/dev/drm/amd/powerplay/hwmgr/vega12_processpptables.c
378
PP_ASSERT_WITH_CODE(pp_table->usStateArrayOffset > 0,
sys/dev/drm/amd/powerplay/hwmgr/vega12_processpptables.c
381
PP_ASSERT_WITH_CODE(state_arrays->ucNumEntries > 0,
sys/dev/drm/amd/powerplay/hwmgr/vega12_processpptables.c
384
PP_ASSERT_WITH_CODE((entry_index <= state_arrays->ucNumEntries),
sys/dev/drm/amd/powerplay/hwmgr/vega12_processpptables.c
68
PP_ASSERT_WITH_CODE((powerplay_table->sHeader.format_revision >=
sys/dev/drm/amd/powerplay/hwmgr/vega12_processpptables.c
71
PP_ASSERT_WITH_CODE(powerplay_table->sHeader.structuresize > 0,
sys/dev/drm/amd/powerplay/hwmgr/vega12_thermal.c
110
PP_ASSERT_WITH_CODE(
sys/dev/drm/amd/powerplay/hwmgr/vega12_thermal.c
124
PP_ASSERT_WITH_CODE(!vega12_disable_fan_control_feature(hwmgr),
sys/dev/drm/amd/powerplay/hwmgr/vega12_thermal.c
34
PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
sys/dev/drm/amd/powerplay/hwmgr/vega12_thermal.c
75
PP_ASSERT_WITH_CODE(!vega12_enable_smc_features(
sys/dev/drm/amd/powerplay/hwmgr/vega12_thermal.c
93
PP_ASSERT_WITH_CODE(!vega12_enable_smc_features(
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
1079
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
1107
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
1136
PP_ASSERT_WITH_CODE(!vega20_od8_get_gfx_clock_base_voltage(hwmgr,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
1144
PP_ASSERT_WITH_CODE(!vega20_od8_get_gfx_clock_base_voltage(hwmgr,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
1152
PP_ASSERT_WITH_CODE(!vega20_od8_get_gfx_clock_base_voltage(hwmgr,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
1235
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
1254
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
1311
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
1351
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
1357
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
1397
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
1403
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
1437
PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
1446
PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
1473
PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
1480
PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
1487
PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
1492
PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
1497
PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
1502
PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
1521
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
1551
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
1556
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
1561
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
1566
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
1571
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
1576
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
1584
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
1589
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
1594
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
1599
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
1604
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
1610
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
1641
PP_ASSERT_WITH_CODE(table != NULL,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
1644
PP_ASSERT_WITH_CODE(table->count > 0,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
1647
PP_ASSERT_WITH_CODE(table->count <= MAX_REGULAR_DPM_NUMBER,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
1673
PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
1683
PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
1690
PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
1701
PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
1709
PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
1720
PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
1731
PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
1752
PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
1763
PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
1774
PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
1781
PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
1792
PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
1803
PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
1831
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
1849
PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
1855
PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
1873
PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_GFXCLK].enabled,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
1879
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
1884
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
1899
PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_UCLK].enabled,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
1905
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
1910
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
1925
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
1941
PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
1959
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
2100
PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
2112
PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
2142
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
2147
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
2174
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
2179
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
2192
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
2197
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
2262
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
2267
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
2289
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
2294
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
2401
PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_GFXCLK].enabled,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
2430
PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_UCLK].enabled,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
2456
PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_DCEFCLK].enabled,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
2479
PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_SOCCLK].enabled,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
2564
PP_ASSERT_WITH_CODE(input, "NULL user input for clock and voltage",
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
2619
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
2729
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
2738
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
2784
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
2789
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
2801
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
2806
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
2872
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
2921
PP_ASSERT_WITH_CODE(dpm_table->count > 0,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
2924
PP_ASSERT_WITH_CODE(dpm_table->count <= NUM_UCLK_DPM_LEVELS,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
2929
PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
2963
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
2998
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
3212
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
3225
PP_ASSERT_WITH_CODE((0 == result),
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
3299
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
3385
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
3439
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
444
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
474
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
479
PP_ASSERT_WITH_CODE(*num_of_levels > 0,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
494
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
499
PP_ASSERT_WITH_CODE(*clk,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
513
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
521
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
541
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
562
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
594
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
621
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
634
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
647
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
660
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
673
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
684
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
695
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
706
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
738
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
762
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
789
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
795
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
816
PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
822
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
874
PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr,
sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
880
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c
640
PP_ASSERT_WITH_CODE((powerplay_table->sHeader.format_revision >=
sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c
643
PP_ASSERT_WITH_CODE(powerplay_table->sHeader.structuresize > 0,
sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c
720
PP_ASSERT_WITH_CODE(
sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c
900
PP_ASSERT_WITH_CODE((hwmgr->pptable != NULL),
sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c
904
PP_ASSERT_WITH_CODE((powerplay_table != NULL),
sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c
908
PP_ASSERT_WITH_CODE((result == 0),
sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c
913
PP_ASSERT_WITH_CODE((result == 0),
sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c
917
PP_ASSERT_WITH_CODE((result == 0),
sys/dev/drm/amd/powerplay/hwmgr/vega20_thermal.c
108
PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr,
sys/dev/drm/amd/powerplay/hwmgr/vega20_thermal.c
42
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/hwmgr/vega20_thermal.c
71
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
1045
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
1188
PP_ASSERT_WITH_CODE((0 == result),
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
1197
PP_ASSERT_WITH_CODE((0 == result),
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
1206
PP_ASSERT_WITH_CODE((0 == result),
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
1315
PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
1365
PP_ASSERT_WITH_CODE(i < hwmgr->dyn_state.mvdd_dependency_on_mclk->count,
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
1405
PP_ASSERT_WITH_CODE(result == 0,
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
1538
PP_ASSERT_WITH_CODE((0 == result),
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
1545
PP_ASSERT_WITH_CODE((0 == result),
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
1577
PP_ASSERT_WITH_CODE((0 == result),
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
1608
PP_ASSERT_WITH_CODE((0 == result),
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
1634
PP_ASSERT_WITH_CODE(result == 0,
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
1730
PP_ASSERT_WITH_CODE(i < SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE,
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
1841
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
1845
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
1969
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
1977
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
1981
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
1985
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
1989
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
1993
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
1997
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
2003
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
2007
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
2019
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
2023
PP_ASSERT_WITH_CODE(0 == result, "Failed to initialize Boot State!", return result);
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
2026
PP_ASSERT_WITH_CODE(0 == result, "Failed to populate BAPM Parameters!", return result);
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
2052
PP_ASSERT_WITH_CODE((1 <= data->dpm_table.pcie_speed_table.count),
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
2060
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
2107
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
2111
PP_ASSERT_WITH_CODE((0 == result),
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
2115
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
2237
PP_ASSERT_WITH_CODE((0 == result), "Failed to upload MC reg table!", return result);
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
2240
PP_ASSERT_WITH_CODE((result == 0),
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
2554
PP_ASSERT_WITH_CODE((table->last <= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE),
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
2556
PP_ASSERT_WITH_CODE((table->num_entries <= MAX_AC_TIMING_ENTRIES),
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
2586
PP_ASSERT_WITH_CODE((j < SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE),
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
2602
PP_ASSERT_WITH_CODE((j < SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE),
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
2618
PP_ASSERT_WITH_CODE((j < SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE),
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
313
PP_ASSERT_WITH_CODE(result == 0,
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
550
PP_ASSERT_WITH_CODE(false,
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
583
PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.cac_leakage_table,
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
585
PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count <= 8,
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
587
PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count == hwmgr->dyn_state.vddc_dependency_on_sclk->count,
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
611
PP_ASSERT_WITH_CODE(data->vddc_voltage_table.count <= 8,
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
771
PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.vddc_dependency_on_sclk,
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
851
PP_ASSERT_WITH_CODE(0 == result, "do not populate SMC VDDC voltage table", return -EINVAL);
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
881
PP_ASSERT_WITH_CODE(result == 0, "do not populate SMC VDDCI voltage table", return -EINVAL);
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
909
PP_ASSERT_WITH_CODE(result == 0, "do not populate SMC mvdd voltage table", return -EINVAL);
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
931
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
935
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
939
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c
956
PP_ASSERT_WITH_CODE((0 == result), "can not get ULV voltage value", return result;);
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
1051
PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt),
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
1153
PP_ASSERT_WITH_CODE((0 == result),
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
1184
PP_ASSERT_WITH_CODE((0 == result),
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
1239
PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
1291
PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
1325
PP_ASSERT_WITH_CODE((0 == result),
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
1339
PP_ASSERT_WITH_CODE(result == 0,
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
1383
PP_ASSERT_WITH_CODE((0 == result),
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
1449
PP_ASSERT_WITH_CODE((0 == result),
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
1486
PP_ASSERT_WITH_CODE((0 == result),
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
1509
PP_ASSERT_WITH_CODE(result == 0,
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
151
PP_ASSERT_WITH_CODE(false,
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
1585
PP_ASSERT_WITH_CODE((0 == result),
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
1592
PP_ASSERT_WITH_CODE((0 == result),
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
1738
PP_ASSERT_WITH_CODE(false,
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
1837
PP_ASSERT_WITH_CODE(false,
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
1954
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
1961
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
1965
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
1969
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
1973
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
1977
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
1981
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
1989
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
1993
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
1997
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
2001
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
2005
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
2011
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
2037
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
2115
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
2119
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
2123
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
2127
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
2290
PP_ASSERT_WITH_CODE((result == 0),
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
230
PP_ASSERT_WITH_CODE(0 == smu7_read_smc_sram_dword(hwmgr,
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
245
PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, vr_config_addr,
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
253
PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, level_addr,
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
266
PP_ASSERT_WITH_CODE(0 == fiji_setup_graphics_level_structure(hwmgr),
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
270
PP_ASSERT_WITH_CODE(0 == smu7_setup_pwr_virus(hwmgr),
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
274
PP_ASSERT_WITH_CODE(0 == fiji_start_avfs_btc(hwmgr),
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
509
PP_ASSERT_WITH_CODE(cac_dtp_table->usTargetOperatingTemp <= 255,
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
615
PP_ASSERT_WITH_CODE(false,
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
702
PP_ASSERT_WITH_CODE(false,
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
708
PP_ASSERT_WITH_CODE(false,
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
713
PP_ASSERT_WITH_CODE(false,
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
717
PP_ASSERT_WITH_CODE(false,
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
724
PP_ASSERT_WITH_CODE(false,
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
730
PP_ASSERT_WITH_CODE(false,
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
736
PP_ASSERT_WITH_CODE(false,
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
742
PP_ASSERT_WITH_CODE(false,
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
749
PP_ASSERT_WITH_CODE(false,
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
790
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
875
PP_ASSERT_WITH_CODE(result == 0,
sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c
960
PP_ASSERT_WITH_CODE((0 == result),
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
1069
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
1243
PP_ASSERT_WITH_CODE((0 == result),
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
1254
PP_ASSERT_WITH_CODE((0 == result),
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
1362
PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
1412
PP_ASSERT_WITH_CODE(i < hwmgr->dyn_state.mvdd_dependency_on_mclk->count,
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
1453
PP_ASSERT_WITH_CODE(result == 0,
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
1597
PP_ASSERT_WITH_CODE(result == 0,
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
163
PP_ASSERT_WITH_CODE((limit >= byte_count), "SMC address is beyond the SMC RAM area.", return -EINVAL);
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
1697
PP_ASSERT_WITH_CODE(i < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE,
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
177
PP_ASSERT_WITH_CODE((0 == byte_count), "SMC size must be divisible by 4.", return -EINVAL);
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
1809
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
1813
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
1923
PP_ASSERT_WITH_CODE(tab->SVI2Enable != (VDDC_ON_SVI2 | VDDCI_ON_SVI2 | MVDD_ON_SVI2) &&
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
1959
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
1967
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
1971
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
1975
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
1979
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
1983
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
1987
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
1993
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
1997
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
2004
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
2008
PP_ASSERT_WITH_CODE(0 == result, "Failed to initialize Boot State!", return result);
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
2011
PP_ASSERT_WITH_CODE(0 == result, "Failed to populate BAPM Parameters!", return result);
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
2035
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
2063
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
2075
PP_ASSERT_WITH_CODE((0 == result),
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
2079
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
2203
PP_ASSERT_WITH_CODE((0 == result), "Failed to upload MC reg table!", return result);
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
2206
PP_ASSERT_WITH_CODE((result == 0),
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
2484
PP_ASSERT_WITH_CODE((table->last <= SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
2486
PP_ASSERT_WITH_CODE((table->num_entries <= MAX_AC_TIMING_ENTRIES),
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
2516
PP_ASSERT_WITH_CODE((j < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
2532
PP_ASSERT_WITH_CODE((j < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
2549
PP_ASSERT_WITH_CODE((j < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
345
PP_ASSERT_WITH_CODE(false,
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
396
PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.cac_leakage_table,
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
398
PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count <= 8,
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
400
PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count == hwmgr->dyn_state.vddc_dependency_on_sclk->count,
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
409
PP_ASSERT_WITH_CODE(false, "Iceland should always support EVV", return -EINVAL);
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
422
PP_ASSERT_WITH_CODE(data->vddc_voltage_table.count <= 8,
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
446
PP_ASSERT_WITH_CODE(false,
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
452
PP_ASSERT_WITH_CODE(false,
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
458
PP_ASSERT_WITH_CODE(false,
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
464
PP_ASSERT_WITH_CODE(false,
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
469
PP_ASSERT_WITH_CODE(false,
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
473
PP_ASSERT_WITH_CODE(false,
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
480
PP_ASSERT_WITH_CODE(false,
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
486
PP_ASSERT_WITH_CODE(false,
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
492
PP_ASSERT_WITH_CODE(false,
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
499
PP_ASSERT_WITH_CODE(false,
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
540
PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.vddc_dependency_on_sclk,
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
629
PP_ASSERT_WITH_CODE(0 == result, "do not populate SMC VDDC voltage table", return -EINVAL);
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
656
PP_ASSERT_WITH_CODE(result == 0, "do not populate SMC VDDCI voltage table", return -EINVAL);
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
681
PP_ASSERT_WITH_CODE(result == 0, "do not populate SMC mvdd voltage table", return -EINVAL);
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
700
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
704
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
708
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
725
PP_ASSERT_WITH_CODE((0 == result), "can not get ULV voltage value", return result;);
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
813
PP_ASSERT_WITH_CODE(result == 0,
sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c
904
PP_ASSERT_WITH_CODE((0 == result),
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
1024
PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt),
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
1090
PP_ASSERT_WITH_CODE((0 == result),
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
1139
PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
1189
PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
1218
PP_ASSERT_WITH_CODE((0 == result),
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
1224
PP_ASSERT_WITH_CODE(result == 0, "Error retrieving Engine Clock dividers from VBIOS.", return result);
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
1253
PP_ASSERT_WITH_CODE((0 == result),
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
129
PP_ASSERT_WITH_CODE(0 == smu7_read_smc_sram_dword(hwmgr,
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
1323
PP_ASSERT_WITH_CODE((0 == result),
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
1346
PP_ASSERT_WITH_CODE(result == 0,
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
140
PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, vr_config_address,
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
1428
PP_ASSERT_WITH_CODE((0 == result),
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
1435
PP_ASSERT_WITH_CODE((0 == result),
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
147
PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address,
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
155
PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address,
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
1582
PP_ASSERT_WITH_CODE(false,
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
1609
PP_ASSERT_WITH_CODE(false,
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
164
PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address,
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
1797
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
180
PP_ASSERT_WITH_CODE(0 == polaris10_setup_graphics_level_structure(hwmgr),
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
1804
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
1808
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
1812
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
1816
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
1820
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
1828
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
1832
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
1836
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
1840
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
1844
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
1850
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
1856
PP_ASSERT_WITH_CODE(0 == result, "Failed to populate AVFS Parameters!", return result;);
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
186
PP_ASSERT_WITH_CODE(0 == smu7_setup_pwr_virus(hwmgr),
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
1880
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
191
PP_ASSERT_WITH_CODE(0 == polaris10_perform_btc(hwmgr),
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
1935
PP_ASSERT_WITH_CODE((result == 0), "Can not find DFS divide id for Sclk", return result);
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
1964
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
1968
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
1972
PP_ASSERT_WITH_CODE(0 == result,
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
2242
PP_ASSERT_WITH_CODE((result == 0),
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
2246
PP_ASSERT_WITH_CODE((result == 0),
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
237
PP_ASSERT_WITH_CODE(false, "SMU Firmware start failed!", return -1);
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
307
PP_ASSERT_WITH_CODE(0, "Failed to load SMU ucode.", return result);
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
441
PP_ASSERT_WITH_CODE(cac_dtp_table->usTargetOperatingTemp <= 255,
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
512
PP_ASSERT_WITH_CODE(false,
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
596
PP_ASSERT_WITH_CODE(false,
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
601
PP_ASSERT_WITH_CODE(false,
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
606
PP_ASSERT_WITH_CODE(false,
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
610
PP_ASSERT_WITH_CODE(false,
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
616
PP_ASSERT_WITH_CODE(false,
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
621
PP_ASSERT_WITH_CODE(false,
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
626
PP_ASSERT_WITH_CODE(false,
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
631
PP_ASSERT_WITH_CODE(false,
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
638
PP_ASSERT_WITH_CODE(false,
sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c
929
PP_ASSERT_WITH_CODE((0 == result),
sys/dev/drm/amd/powerplay/smumgr/smu10_smumgr.c
121
PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE,
sys/dev/drm/amd/powerplay/smumgr/smu10_smumgr.c
123
PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0,
sys/dev/drm/amd/powerplay/smumgr/smu10_smumgr.c
125
PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,
sys/dev/drm/amd/powerplay/smumgr/smu10_smumgr.c
149
PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE,
sys/dev/drm/amd/powerplay/smumgr/smu10_smumgr.c
151
PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0,
sys/dev/drm/amd/powerplay/smumgr/smu10_smumgr.c
153
PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,
sys/dev/drm/amd/powerplay/smumgr/smu7_smumgr.c
392
PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
sys/dev/drm/amd/powerplay/smumgr/smu7_smumgr.c
395
PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
sys/dev/drm/amd/powerplay/smumgr/smu7_smumgr.c
398
PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
sys/dev/drm/amd/powerplay/smumgr/smu7_smumgr.c
40
PP_ASSERT_WITH_CODE((0 == (3 & smc_addr)), "SMC address must be 4 byte aligned.", return -EINVAL);
sys/dev/drm/amd/powerplay/smumgr/smu7_smumgr.c
401
PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
sys/dev/drm/amd/powerplay/smumgr/smu7_smumgr.c
404
PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
sys/dev/drm/amd/powerplay/smumgr/smu7_smumgr.c
407
PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
sys/dev/drm/amd/powerplay/smumgr/smu7_smumgr.c
41
PP_ASSERT_WITH_CODE((limit > (smc_addr + 3)), "SMC addr is beyond the SMC RAM area.", return -EINVAL);
sys/dev/drm/amd/powerplay/smumgr/smu7_smumgr.c
410
PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
sys/dev/drm/amd/powerplay/smumgr/smu7_smumgr.c
413
PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
sys/dev/drm/amd/powerplay/smumgr/smu7_smumgr.c
416
PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
sys/dev/drm/amd/powerplay/smumgr/smu7_smumgr.c
420
PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
sys/dev/drm/amd/powerplay/smumgr/smu7_smumgr.c
465
PP_ASSERT_WITH_CODE((limit >= byte_count), "SMC address is beyond the SMC RAM area.", return -EINVAL);
sys/dev/drm/amd/powerplay/smumgr/smu7_smumgr.c
475
PP_ASSERT_WITH_CODE((0 == byte_count), "SMC size must be divisible by 4.", return -EINVAL);
sys/dev/drm/amd/powerplay/smumgr/smu7_smumgr.c
57
PP_ASSERT_WITH_CODE((0 == (3 & smc_start_address)), "SMC address must be 4 byte aligned.", return -EINVAL);
sys/dev/drm/amd/powerplay/smumgr/smu7_smumgr.c
58
PP_ASSERT_WITH_CODE((limit > (smc_start_address + byte_count)), "SMC address is beyond the SMC RAM area.", return -EINVAL);
sys/dev/drm/amd/powerplay/smumgr/smu7_smumgr.c
94
PP_ASSERT_WITH_CODE((0 == (3 & smc_start_address)), "SMC address must be 4 byte aligned.", return -EINVAL);
sys/dev/drm/amd/powerplay/smumgr/smu7_smumgr.c
95
PP_ASSERT_WITH_CODE((limit > (smc_start_address + byte_count)), "SMC address is beyond the SMC RAM area.", return -EINVAL);
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
1108
PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
1162
PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
1201
PP_ASSERT_WITH_CODE(result == 0,
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
1344
PP_ASSERT_WITH_CODE((!result),
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
1352
PP_ASSERT_WITH_CODE((!result),
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
1401
PP_ASSERT_WITH_CODE((!result),
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
1446
PP_ASSERT_WITH_CODE((!result),
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
1472
PP_ASSERT_WITH_CODE(result == 0,
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
1661
PP_ASSERT_WITH_CODE(false,
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
1843
PP_ASSERT_WITH_CODE(cac_dtp_table->usTargetOperatingTemp <= 255,
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
1920
PP_ASSERT_WITH_CODE(false,
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
2006
PP_ASSERT_WITH_CODE(false,
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
2012
PP_ASSERT_WITH_CODE(false,
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
2017
PP_ASSERT_WITH_CODE(false,
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
2022
PP_ASSERT_WITH_CODE(false,
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
2028
PP_ASSERT_WITH_CODE(false,
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
2034
PP_ASSERT_WITH_CODE(false,
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
2041
PP_ASSERT_WITH_CODE(false,
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
2047
PP_ASSERT_WITH_CODE(
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
2056
PP_ASSERT_WITH_CODE(false,
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
2072
PP_ASSERT_WITH_CODE(
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
2191
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
2196
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
2260
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
2269
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
2273
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
2277
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
2281
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
2285
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
2289
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
2297
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
2302
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
2306
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
2310
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
2316
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
2346
PP_ASSERT_WITH_CODE((1 <= data->dpm_table.pcie_speed_table.count),
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
2355
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
2442
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
2446
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
2450
PP_ASSERT_WITH_CODE((!result),
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
2454
PP_ASSERT_WITH_CODE((!result),
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
2592
PP_ASSERT_WITH_CODE((!result),
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
2597
PP_ASSERT_WITH_CODE((result == 0),
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
2946
PP_ASSERT_WITH_CODE((table->last <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
2948
PP_ASSERT_WITH_CODE((table->num_entries <= MAX_AC_TIMING_ENTRIES),
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
2978
PP_ASSERT_WITH_CODE((j < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
2995
PP_ASSERT_WITH_CODE((j < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
3011
PP_ASSERT_WITH_CODE((j < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
451
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
456
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
461
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
466
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
471
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
555
PP_ASSERT_WITH_CODE(result == 0,
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
637
PP_ASSERT_WITH_CODE((!result),
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
735
PP_ASSERT_WITH_CODE((pcie_entry_count >= 1),
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
811
PP_ASSERT_WITH_CODE(
sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c
986
PP_ASSERT_WITH_CODE(
sys/dev/drm/amd/powerplay/smumgr/vega10_smumgr.c
147
PP_ASSERT_WITH_CODE(!smu9_send_msg_to_smc(hwmgr,
sys/dev/drm/amd/powerplay/smumgr/vega10_smumgr.c
326
PP_ASSERT_WITH_CODE(!vega10_verify_smc_interface(hwmgr),
sys/dev/drm/amd/powerplay/smumgr/vega10_smumgr.c
41
PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE,
sys/dev/drm/amd/powerplay/smumgr/vega10_smumgr.c
43
PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0,
sys/dev/drm/amd/powerplay/smumgr/vega10_smumgr.c
45
PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,
sys/dev/drm/amd/powerplay/smumgr/vega10_smumgr.c
68
PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE,
sys/dev/drm/amd/powerplay/smumgr/vega10_smumgr.c
70
PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0,
sys/dev/drm/amd/powerplay/smumgr/vega10_smumgr.c
72
PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,
sys/dev/drm/amd/powerplay/smumgr/vega12_smumgr.c
104
PP_ASSERT_WITH_CODE(smu9_send_msg_to_smc_with_parameter(hwmgr,
sys/dev/drm/amd/powerplay/smumgr/vega12_smumgr.c
122
PP_ASSERT_WITH_CODE(smu9_send_msg_to_smc_with_parameter(hwmgr,
sys/dev/drm/amd/powerplay/smumgr/vega12_smumgr.c
126
PP_ASSERT_WITH_CODE(smu9_send_msg_to_smc_with_parameter(hwmgr,
sys/dev/drm/amd/powerplay/smumgr/vega12_smumgr.c
131
PP_ASSERT_WITH_CODE(smu9_send_msg_to_smc_with_parameter(hwmgr,
sys/dev/drm/amd/powerplay/smumgr/vega12_smumgr.c
135
PP_ASSERT_WITH_CODE(smu9_send_msg_to_smc_with_parameter(hwmgr,
sys/dev/drm/amd/powerplay/smumgr/vega12_smumgr.c
152
PP_ASSERT_WITH_CODE(smu9_send_msg_to_smc(hwmgr,
sys/dev/drm/amd/powerplay/smumgr/vega12_smumgr.c
158
PP_ASSERT_WITH_CODE(smu9_send_msg_to_smc(hwmgr,
sys/dev/drm/amd/powerplay/smumgr/vega12_smumgr.c
345
PP_ASSERT_WITH_CODE(smu9_is_smc_ram_running(hwmgr),
sys/dev/drm/amd/powerplay/smumgr/vega12_smumgr.c
46
PP_ASSERT_WITH_CODE(table_id < TABLE_COUNT,
sys/dev/drm/amd/powerplay/smumgr/vega12_smumgr.c
48
PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0,
sys/dev/drm/amd/powerplay/smumgr/vega12_smumgr.c
50
PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,
sys/dev/drm/amd/powerplay/smumgr/vega12_smumgr.c
52
PP_ASSERT_WITH_CODE(smu9_send_msg_to_smc_with_parameter(hwmgr,
sys/dev/drm/amd/powerplay/smumgr/vega12_smumgr.c
56
PP_ASSERT_WITH_CODE(smu9_send_msg_to_smc_with_parameter(hwmgr,
sys/dev/drm/amd/powerplay/smumgr/vega12_smumgr.c
61
PP_ASSERT_WITH_CODE(smu9_send_msg_to_smc_with_parameter(hwmgr,
sys/dev/drm/amd/powerplay/smumgr/vega12_smumgr.c
84
PP_ASSERT_WITH_CODE(table_id < TABLE_COUNT,
sys/dev/drm/amd/powerplay/smumgr/vega12_smumgr.c
86
PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0,
sys/dev/drm/amd/powerplay/smumgr/vega12_smumgr.c
88
PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,
sys/dev/drm/amd/powerplay/smumgr/vega12_smumgr.c
94
PP_ASSERT_WITH_CODE(smu9_send_msg_to_smc_with_parameter(hwmgr,
sys/dev/drm/amd/powerplay/smumgr/vega12_smumgr.c
99
PP_ASSERT_WITH_CODE(smu9_send_msg_to_smc_with_parameter(hwmgr,
sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c
170
PP_ASSERT_WITH_CODE(table_id < TABLE_COUNT,
sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c
172
PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0,
sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c
174
PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,
sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c
177
PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c
182
PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c
187
PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c
210
PP_ASSERT_WITH_CODE(table_id < TABLE_COUNT,
sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c
212
PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0,
sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c
214
PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,
sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c
220
PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c
225
PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c
230
PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c
248
PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c
253
PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c
258
PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c
273
PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c
278
PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c
283
PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c
305
PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c
309
PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c
314
PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c
318
PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c
336
PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc(hwmgr,
sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c
341
PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc(hwmgr,
sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c
539
PP_ASSERT_WITH_CODE(ret,
sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c
544
PP_ASSERT_WITH_CODE(!ret,
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
1048
PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
1099
PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
1129
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
1136
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
1167
PP_ASSERT_WITH_CODE((0 == result),
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
1242
PP_ASSERT_WITH_CODE((0 == result),
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
1268
PP_ASSERT_WITH_CODE(result == 0,
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
1354
PP_ASSERT_WITH_CODE((0 == result),
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
1361
PP_ASSERT_WITH_CODE((0 == result),
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
140
PP_ASSERT_WITH_CODE(false, "SMU Firmware start failed!", return -1);
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
1461
PP_ASSERT_WITH_CODE(cac_dtp_table->usTargetOperatingTemp <= 255,
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
1543
PP_ASSERT_WITH_CODE(false,
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
1691
PP_ASSERT_WITH_CODE(false,
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
1717
PP_ASSERT_WITH_CODE(false,
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
1779
PP_ASSERT_WITH_CODE(false,
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
1863
PP_ASSERT_WITH_CODE(false,
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
1868
PP_ASSERT_WITH_CODE(false,
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
1873
PP_ASSERT_WITH_CODE(false,
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
1877
PP_ASSERT_WITH_CODE(false,
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
1883
PP_ASSERT_WITH_CODE(false,
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
1888
PP_ASSERT_WITH_CODE(false,
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
1893
PP_ASSERT_WITH_CODE(false,
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
1898
PP_ASSERT_WITH_CODE(false,
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
1906
PP_ASSERT_WITH_CODE(false,
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
1961
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
1968
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
1972
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
1976
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
1980
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
1984
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
1992
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
1996
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
2000
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
2004
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
2008
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
2014
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
2020
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
2041
PP_ASSERT_WITH_CODE(hw_data->dpm_table.pcie_speed_table.count >= 1,
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
2050
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
2113
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
212
PP_ASSERT_WITH_CODE(0, "Failed to load SMU ucode.", return result);
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
2146
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
2150
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
2154
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
2242
PP_ASSERT_WITH_CODE((result == 0),
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
2246
PP_ASSERT_WITH_CODE((result == 0),
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
2273
PP_ASSERT_WITH_CODE(hwmgr->thermal_controller.fanInfo.bNoFan,
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
795
PP_ASSERT_WITH_CODE((clock >= min),
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
825
PP_ASSERT_WITH_CODE((0 == result),
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
916
PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt),
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
966
PP_ASSERT_WITH_CODE(!atomctrl_get_memory_pll_dividers_ai(hwmgr,
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
993
PP_ASSERT_WITH_CODE(!result,
sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c
999
PP_ASSERT_WITH_CODE(!result,
