PPCLK_VCLK
(PPCLK_VCLK << 16) | (min_freq & 0xffff))),
(PPCLK_VCLK << 16) | (max_freq & 0xffff))),
ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_VCLK);
(PPCLK_VCLK << 16) | (min_freq & 0xffff))),
(PPCLK_VCLK << 16) | (max_freq & 0xffff))),
ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_VCLK);
pptable->DpmDescriptor[PPCLK_VCLK].VoltageMode,
pptable->DpmDescriptor[PPCLK_VCLK].SnapToDiscrete,
pptable->DpmDescriptor[PPCLK_VCLK].NumDiscreteLevels,
pptable->DpmDescriptor[PPCLK_VCLK].padding,
pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.m,
pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.b,
pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.a,
pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.b,
pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.c);
pr_info("DcModeMaxFreq[PPCLK_VCLK] = %d\n", pptable->DcModeMaxFreq[PPCLK_VCLK]);