PPCLK_UCLK
(PPCLK_UCLK << 16) | (min_freq & 0xffff))),
(PPCLK_UCLK << 16) | (min_freq & 0xffff))),
(PPCLK_UCLK << 16) | (max_freq & 0xffff))),
vega12_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, false) == 0,
vega12_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, true) == 0,
smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetDpmClockFreq, (PPCLK_UCLK << 16)) == 0,
(PPCLK_UCLK << 16 ) | dpm_table->dpm_state.hard_min_level)),
ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_UCLK);
PPCLK_UCLK)) == 0,
(PPCLK_UCLK << 16) | (min_freq & 0xffff))),
(PPCLK_UCLK << 16) | (min_freq & 0xffff))),
(PPCLK_UCLK << 16) | (max_freq & 0xffff))),
ret = vega20_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, false);
ret = vega20_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, true);
PPCLK_UCLK,
(PPCLK_UCLK << 16 ) | dpm_table->dpm_state.hard_min_level)),
ret = vega20_get_current_clk_freq(hwmgr, PPCLK_UCLK, &now);
(PPCLK_UCLK << 16 ) | dpm_table->dpm_state.hard_min_level)),
ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_UCLK);
pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
pptable->DpmDescriptor[PPCLK_UCLK].padding,
pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c);
pr_info("DcModeMaxFreq[PPCLK_UCLK] = %d\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);