PPCLK_GFXCLK
(PPCLK_GFXCLK << 16) | (min_freq & 0xffff))),
(PPCLK_GFXCLK << 16) | (max_freq & 0xffff))),
vega12_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, false) == 0,
vega12_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, true) == 0,
PPSMC_MSG_GetDpmClockFreq, (PPCLK_GFXCLK << 16)) == 0,
ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_GFXCLK);
(PPCLK_GFXCLK << 16) | (min_freq & 0xffff))),
(PPCLK_GFXCLK << 16) | (max_freq & 0xffff))),
ret = vega20_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, false);
ret = vega20_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, true);
PPCLK_GFXCLK,
ret = vega20_get_current_clk_freq(hwmgr, PPCLK_GFXCLK, &now);
ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_GFXCLK);
pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
pptable->DpmDescriptor[PPCLK_GFXCLK].padding,
pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c);
pr_info("DcModeMaxFreq[PPCLK_GFXCLK] = %d\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);