POSTING_READ
POSTING_READ(VLV_GTLC_WAKE_CTRL);
POSTING_READ(fence_reg_lo);
POSTING_READ(fence_reg_lo);
POSTING_READ(reg);
POSTING_READ(reg);
POSTING_READ(GFX_FLSH_CNTL_GEN6);
POSTING_READ(GEN8_##type##_IMR(which)); \
POSTING_READ(GEN7_MISCCPCTL);
POSTING_READ(GEN8_##type##_IIR(which)); \
POSTING_READ(reg);
POSTING_READ(GEN8_##type##_IIR(which)); \
POSTING_READ(type##IMR); \
POSTING_READ(type##IIR); \
POSTING_READ(type##IIR); \
POSTING_READ(reg);
POSTING_READ(reg);
POSTING_READ(GEN8_##type##_IMR(which)); \
POSTING_READ(type##IMR); \
POSTING_READ(DEIMR);
POSTING_READ(GEN8_RING_FAULT_REG);
POSTING_READ(RING_FAULT_REG(dev_priv->engine[RCS]));
POSTING_READ(SDEIER);
POSTING_READ(VLV_MASTER_IER);
POSTING_READ(GEN8_MASTER_IRQ);
POSTING_READ(GEN11_GFX_MSTR_IRQ);
POSTING_READ(GEN8_MASTER_IRQ);
POSTING_READ(GEN11_DE_HPD_IMR);
POSTING_READ(gen6_pm_imr(dev_priv));
POSTING_READ(VLV_MASTER_IER);
POSTING_READ(GEN8_MASTER_IRQ);
POSTING_READ(SDEIER);
POSTING_READ(GEN11_GFX_MSTR_IRQ);
POSTING_READ(GEN8_MASTER_IRQ);
POSTING_READ(reg);
POSTING_READ(GEN8_DE_PORT_IMR);
POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
POSTING_READ(SDEIMR);
POSTING_READ(reg);
POSTING_READ(reg);
POSTING_READ(ICL_DSI_ESC_CLK_DIV(port));
POSTING_READ(ICL_DPHY_ESC_CLK_DIV(port));
POSTING_READ(CDCLK_CTL);
POSTING_READ(CDCLK_CTL);
POSTING_READ(DPLL_CTRL1);
POSTING_READ(GAMMA_MODE(pipe));
POSTING_READ(GAMMA_MODE(pipe));
POSTING_READ(crt->adpa_reg);
POSTING_READ(pipeconf_reg);
POSTING_READ(crt->adpa_reg);
POSTING_READ(DC_STATE_DEBUG);
POSTING_READ(FDI_RX_CTL(PIPE_A));
POSTING_READ(DDI_BUF_CTL(PORT_E));
POSTING_READ(FDI_RX_CTL(PIPE_A));
POSTING_READ(FDI_RX_MISC(PIPE_A));
POSTING_READ(FDI_RX_CTL(PIPE_A));
POSTING_READ(DDI_BUF_CTL(PORT_E));
POSTING_READ(DP_TP_CTL(PORT_E));
POSTING_READ(FDI_RX_MISC(PIPE_A));
POSTING_READ(DPCLKA_CFGCR0_ICL);
POSTING_READ(CHICKEN_TRANS(transcoder));
POSTING_READ(DP_TP_CTL(port));
POSTING_READ(DP_TP_CTL(port));
POSTING_READ(DDI_BUF_CTL(port));
POSTING_READ(DPLL(pipe));
POSTING_READ(DPLL_MD(pipe));
POSTING_READ(DPLL_MD(pipe));
POSTING_READ(vga_reg);
POSTING_READ(reg);
POSTING_READ(DPLL(pipe));
POSTING_READ(DPLL(pipe));
POSTING_READ(PIPECONF(pipe));
POSTING_READ(PIPECONF(pipe));
POSTING_READ(DPLL(pipe));
POSTING_READ(reg);
POSTING_READ(DPLL(pipe));
POSTING_READ(DPLL(pipe));
POSTING_READ(DPLL(pipe));
POSTING_READ(reg);
POSTING_READ(reg);
POSTING_READ(reg);
POSTING_READ(reg);
POSTING_READ(reg);
POSTING_READ(reg);
POSTING_READ(reg);
POSTING_READ(reg);
POSTING_READ(reg);
POSTING_READ(reg);
POSTING_READ(reg);
POSTING_READ(reg);
POSTING_READ(reg);
POSTING_READ(reg);
POSTING_READ(reg);
POSTING_READ(reg);
POSTING_READ(reg);
POSTING_READ(reg);
POSTING_READ(reg);
POSTING_READ(reg);
POSTING_READ(SOUTH_CHICKEN1);
POSTING_READ(IPS_CTL);
POSTING_READ(PIPECONF(intel_crtc->pipe));
POSTING_READ(PCH_DREF_CONTROL);
POSTING_READ(PCH_DREF_CONTROL);
POSTING_READ(PCH_DREF_CONTROL);
POSTING_READ(PCH_DREF_CONTROL);
POSTING_READ(PIPECONF(pipe));
POSTING_READ(PIPECONF(cpu_transcoder));
POSTING_READ(D_COMP_BDW);
POSTING_READ(LCPLL_CTL);
POSTING_READ(LCPLL_CTL);
POSTING_READ(LCPLL_CTL);
POSTING_READ(pp_ctrl_reg);
POSTING_READ(pp_ctrl_reg);
POSTING_READ(pp_ctrl_reg);
POSTING_READ(pp_ctrl_reg);
POSTING_READ(pp_ctrl_reg);
POSTING_READ(pp_ctrl_reg);
POSTING_READ(pp_ctrl_reg);
POSTING_READ(pp_ctrl_reg);
POSTING_READ(DP_A);
POSTING_READ(DP_A);
POSTING_READ(DP_A);
POSTING_READ(intel_dp->output_reg);
POSTING_READ(pp_on_reg);
POSTING_READ(intel_dp->output_reg);
POSTING_READ(intel_dp->output_reg);
POSTING_READ(intel_dp->output_reg);
POSTING_READ(intel_dp->output_reg);
POSTING_READ(intel_dp->output_reg);
POSTING_READ(intel_dp->output_reg);
POSTING_READ(intel_dp->output_reg);
POSTING_READ(intel_dp->output_reg);
POSTING_READ(intel_dp->output_reg);
POSTING_READ(BXT_PORT_PLL_ENABLE(port));
POSTING_READ(BXT_PORT_PLL_ENABLE(port));
POSTING_READ(CNL_DPLL_CFGCR0(id));
POSTING_READ(CNL_DPLL_CFGCR1(id));
POSTING_READ(ICL_DPLL_CFGCR1(id));
POSTING_READ(MG_PLL_TDC_COLDST_BIAS(port));
POSTING_READ(PCH_DPLL(id));
POSTING_READ(PCH_DPLL(id));
POSTING_READ(PCH_DPLL(id));
POSTING_READ(WRPLL_CTL(id));
POSTING_READ(SPLL_CTL);
POSTING_READ(WRPLL_CTL(id));
POSTING_READ(SPLL_CTL);
POSTING_READ(DPLL_CTRL1);
POSTING_READ(regs[id].cfgcr1);
POSTING_READ(regs[id].cfgcr2);
POSTING_READ(regs[id].ctl);
POSTING_READ(MSG_FBC_REND_STATE);
POSTING_READ(reg);
POSTING_READ(reg);
POSTING_READ(GEN7_ERR_INT);
POSTING_READ(SERR_INT);
POSTING_READ(guc_send_reg(guc, i - 1));
POSTING_READ(intel_hdmi->hdmi_reg);
POSTING_READ(intel_hdmi->hdmi_reg);
POSTING_READ(intel_hdmi->hdmi_reg);
POSTING_READ(intel_hdmi->hdmi_reg);
POSTING_READ(intel_hdmi->hdmi_reg);
POSTING_READ(intel_hdmi->hdmi_reg);
POSTING_READ(intel_hdmi->hdmi_reg);
POSTING_READ(intel_hdmi->hdmi_reg);
POSTING_READ(intel_hdmi->hdmi_reg);
POSTING_READ(intel_hdmi->hdmi_reg);
POSTING_READ(intel_hdmi->hdmi_reg);
POSTING_READ(intel_hdmi->hdmi_reg);
POSTING_READ(intel_hdmi->hdmi_reg);
POSTING_READ(VIDEO_DIP_CTL);
POSTING_READ(reg);
POSTING_READ(reg);
POSTING_READ(reg);
POSTING_READ(ctl_reg);
POSTING_READ(reg);
POSTING_READ(reg);
POSTING_READ(reg);
POSTING_READ(reg);
POSTING_READ(reg);
POSTING_READ(reg);
POSTING_READ(reg);
POSTING_READ(reg);
POSTING_READ(reg);
POSTING_READ(reg);
POSTING_READ(bus->gpio_reg);
POSTING_READ(bus->gpio_reg);
POSTING_READ(RING_HWS_PGA(engine->mmio_base));
POSTING_READ(lvds_encoder->reg);
POSTING_READ(lvds_encoder->reg);
POSTING_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
POSTING_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
POSTING_READ(BLC_PWM_PCH_CTL1);
POSTING_READ(BLC_PWM_CPU_CTL2);
POSTING_READ(BLC_PWM_PCH_CTL1);
POSTING_READ(BLC_PWM_CTL);
POSTING_READ(BLC_PWM_CTL2);
POSTING_READ(VLV_BLC_PWM_CTL2(pipe));
POSTING_READ(DSPFW1);
POSTING_READ(FW_BLC_SELF_VLV);
POSTING_READ(FW_BLC_SELF);
POSTING_READ(DSPFW3);
POSTING_READ(FW_BLC_SELF);
POSTING_READ(INSTPM);
POSTING_READ(VIDSTART);
POSTING_READ(ECR);
POSTING_READ(DSPSURF(pipe));
POSTING_READ(GEN8_L3SQCREG1);
POSTING_READ(DSPFW1);
POSTING_READ(mmio);
POSTING_READ(reg);
POSTING_READ(DBUF_CTL_S2);
POSTING_READ(DBUF_CTL_S2);
POSTING_READ(intel_sdvo->sdvo_reg);
POSTING_READ(intel_sdvo->sdvo_reg);
POSTING_READ(GEN3_SDVOB);
POSTING_READ(GEN3_SDVOC);
POSTING_READ(TV_DAC);
POSTING_READ(TV_CTL);
POSTING_READ(VDECCLK_GATE_D);
POSTING_READ(VDECCLK_GATE_D);
POSTING_READ(ILK_GDSR);
POSTING_READ(port_ctrl);
POSTING_READ(port_ctrl);
POSTING_READ(BXT_DSI_PLL_CTL);