PORT_DSP_DATA
AGG_WR(ch->parent, PORT_DSP_DATA, cp1, 2);
AGG_WR(ch->parent, PORT_DSP_DATA, cp1, 2);
return AGG_RD(ess, PORT_DSP_DATA, 2);
AGG_WR(ess, PORT_DSP_DATA, data, 2);
while (AGG_RD(ess, PORT_DSP_DATA, 2) != data) {
AGG_WR(ess, PORT_DSP_DATA, data, 2);