sys/dev/drm/i915/i915_cmd_parser.c

617

REG32(GEN7_PIPE_DE_LOAD_SL(PIPE_B)),

sys/dev/drm/i915/i915_irq.c

1905

case PIPE_B:

sys/dev/drm/i915/i915_irq.c

2342

intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B);

sys/dev/drm/i915/i915_irq.c

4375

i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);

sys/dev/drm/i915/i915_irq.c

4553

i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);

sys/dev/drm/i915/i915_irq.c

4676

i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);

sys/dev/drm/i915/i915_irq.c

761

i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);

sys/dev/drm/i915/i915_reg.h

10451

#define ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10454

#define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10472

#define ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10475

#define ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10486

#define ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10489

#define ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10501

#define ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10504

#define ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10516

#define ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10519

#define ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10531

#define ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10534

#define ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10546

#define ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10549

#define ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10563

#define ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10566

#define ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10578

#define ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10581

#define ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10593

#define ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10596

#define ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10608

#define ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10611

#define ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10625

#define ICL_DSC0_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10628

#define ICL_DSC1_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10638

#define ICL_DSC0_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10641

#define ICL_DSC1_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10651

#define ICL_DSC0_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10654

#define ICL_DSC1_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10664

#define ICL_DSC0_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10667

#define ICL_DSC1_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10677

#define ICL_DSC0_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10680

#define ICL_DSC1_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10690

#define ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10693

#define ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10712

#define ICL_DSC0_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10715

#define ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10718

#define ICL_DSC1_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10721

#define ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10737

#define ICL_DSC0_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10740

#define ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10743

#define ICL_DSC1_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10746

#define ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

7691

#define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

7694

#define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

7697

#define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

7700

#define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

7719

#define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

7722

#define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

7725

#define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

7728

#define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

7744

#define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

7747

#define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

7750

#define ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

7753

#define ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

7769

#define ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

7772

#define ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

7775

#define ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

7778

#define ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/intel_ddi.c

1856

case PIPE_B:

sys/dev/drm/i915/intel_ddi.c

2031

*pipe = PIPE_B;

sys/dev/drm/i915/intel_device_info.c

749

info->num_scalers[PIPE_B] = 2;

sys/dev/drm/i915/intel_device_info.c

769

info->num_sprites[PIPE_B] = 2;

sys/dev/drm/i915/intel_device_info.c

816

disabled_mask |= BIT(PIPE_B);

sys/dev/drm/i915/intel_device_info.c

824

case BIT(PIPE_B):

sys/dev/drm/i915/intel_device_info.c

825

case BIT(PIPE_A) | BIT(PIPE_B):

sys/dev/drm/i915/intel_display.c

1342

I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,

sys/dev/drm/i915/intel_display.c

1360

I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,

sys/dev/drm/i915/intel_display.c

13934

} else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {

sys/dev/drm/i915/intel_display.c

1480

I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);

sys/dev/drm/i915/intel_display.c

1488

WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);

sys/dev/drm/i915/intel_display.c

15559

WARN_ON(I915_READ(CURCNTR(PIPE_B)) & MCURSOR_MODE);

sys/dev/drm/i915/intel_display.c

1577

I915_WRITE(DPLL(PIPE_B),

sys/dev/drm/i915/intel_display.c

1578

I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);

sys/dev/drm/i915/intel_display.c

4651

WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);

sys/dev/drm/i915/intel_display.c

4670

case PIPE_B:

sys/dev/drm/i915/intel_display.c

6137

if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {

sys/dev/drm/i915/intel_display.c

6538

case PIPE_B:

sys/dev/drm/i915/intel_display.c

6561

other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);

sys/dev/drm/i915/intel_display.c

7063

if (pipe == PIPE_B)

sys/dev/drm/i915/intel_display.c

7459

(pipe == PIPE_B || pipe == PIPE_C))

sys/dev/drm/i915/intel_display.c

7811

if (crtc->pipe != PIPE_B)

sys/dev/drm/i915/intel_display.c

7891

if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B &&

sys/dev/drm/i915/intel_display.c

9537

trans_edp_pipe = PIPE_B;

sys/dev/drm/i915/intel_dp.c

3252

if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))

sys/dev/drm/i915/intel_dp.c

3860

if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {

sys/dev/drm/i915/intel_dp.c

6507

if (pipe != PIPE_A && pipe != PIPE_B)

sys/dev/drm/i915/intel_dp.c

6510

if (pipe != PIPE_A && pipe != PIPE_B)

sys/dev/drm/i915/intel_dp.c

784

unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);

sys/dev/drm/i915/intel_dp.c

913

for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {

sys/dev/drm/i915/intel_dpio_phy.c

795

if (ch == DPIO_CH0 && pipe == PIPE_B)

sys/dev/drm/i915/intel_dpio_phy.c

807

if (pipe != PIPE_B) {

sys/dev/drm/i915/intel_dpio_phy.c

828

if (pipe != PIPE_B)

sys/dev/drm/i915/intel_dpio_phy.c

837

if (pipe != PIPE_B)

sys/dev/drm/i915/intel_dpio_phy.c

850

if (pipe != PIPE_B)

sys/dev/drm/i915/intel_dpio_phy.c

960

if (pipe != PIPE_B) {

sys/dev/drm/i915/intel_drv.h

1243

case PIPE_B:

sys/dev/drm/i915/intel_hdmi.c

1413

if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {

sys/dev/drm/i915/intel_panel.c

1640

if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))

sys/dev/drm/i915/intel_panel.c

499

if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))

sys/dev/drm/i915/intel_pm.c

1000

FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |

sys/dev/drm/i915/intel_pm.c

1001

FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));

sys/dev/drm/i915/intel_pm.c

1013

FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) |

sys/dev/drm/i915/intel_pm.c

1014

FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) |

sys/dev/drm/i915/intel_pm.c

1015

FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) |

sys/dev/drm/i915/intel_pm.c

1021

FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |

sys/dev/drm/i915/intel_pm.c

1022

FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));

sys/dev/drm/i915/intel_pm.c

1025

FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) |

sys/dev/drm/i915/intel_pm.c

1026

FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) |

sys/dev/drm/i915/intel_pm.c

1027

FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) |

sys/dev/drm/i915/intel_pm.c

1988

case PIPE_B:

sys/dev/drm/i915/intel_pm.c

3550

if (dirty & WM_DIRTY_PIPE(PIPE_B))

sys/dev/drm/i915/intel_pm.c

3557

if (dirty & WM_DIRTY_LINETIME(PIPE_B))

sys/dev/drm/i915/intel_pm.c

3558

I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);

sys/dev/drm/i915/intel_pm.c

488

case PIPE_B:

sys/dev/drm/i915/intel_pm.c

5627

[PIPE_B] = WM0_PIPEB_ILK,

sys/dev/drm/i915/intel_pm.c

5680

wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB);

sys/dev/drm/i915/intel_pm.c

5681

wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEB);

sys/dev/drm/i915/intel_pm.c

5688

wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEB);

sys/dev/drm/i915/intel_pm.c

5720

wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB);

sys/dev/drm/i915/intel_pm.c

5721

wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEB);

sys/dev/drm/i915/intel_pm.c

5734

wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);

sys/dev/drm/i915/intel_pm.c

5735

wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);

sys/dev/drm/i915/intel_pm.c

5750

wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8;

sys/dev/drm/i915/intel_pm.c

5751

wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8;

sys/dev/drm/i915/intel_pm.c

5752

wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8;

sys/dev/drm/i915/intel_pm.c

5758

wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);

sys/dev/drm/i915/intel_pm.c

5759

wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);

sys/dev/drm/i915/intel_pm.c

5763

wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8;

sys/dev/drm/i915/intel_pm.c

5764

wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8;

sys/dev/drm/i915/intel_pm.c

5765

wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8;

sys/dev/drm/i915/intel_pm.c

938

FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |

sys/dev/drm/i915/intel_pm.c

939

FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |

sys/dev/drm/i915/intel_pm.c

945

FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEB) |

sys/dev/drm/i915/intel_pm.c

988

FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |

sys/dev/drm/i915/intel_pm.c

989

FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |

sys/dev/drm/i915/intel_runtime_pm.c

1158

(I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0)

sys/dev/drm/i915/intel_runtime_pm.c

1288

assert_pll_disabled(dev_priv, PIPE_B);

sys/dev/drm/i915/intel_runtime_pm.c

2139

.hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),

sys/dev/drm/i915/intel_runtime_pm.c

2338

.hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),

sys/dev/drm/i915/intel_runtime_pm.c

2418

.hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),

sys/dev/drm/i915/intel_runtime_pm.c

2477

.hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),

sys/dev/drm/i915/intel_runtime_pm.c

2645

.hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),

sys/dev/drm/i915/intel_runtime_pm.c

2776

.hsw.irq_pipe_mask = BIT(PIPE_B),

sys/dev/drm/i915/intel_runtime_pm.c

846

if ((I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE) == 0)

sys/dev/drm/i915/intel_runtime_pm.c

847

i830_enable_pipe(dev_priv, PIPE_B);

sys/dev/drm/i915/intel_runtime_pm.c

853

i830_disable_pipe(dev_priv, PIPE_B);

sys/dev/drm/i915/intel_runtime_pm.c

861

I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE;

sys/dev/drm/i915/intel_sdvo.c

1553

if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {

sys/dev/drm/i915/intel_sprite.c

1862

} else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {

sys/dev/drm/i915/intel_sprite.c

656

if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B)

sys/dev/drm/i915/vlv_dsi.c

1053

enabled = I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE;

sys/dev/drm/i915/vlv_dsi.c

1077

*pipe = port == PORT_A ? PIPE_A : PIPE_B;

sys/dev/drm/i915/vlv_dsi.c

1695

if (connector->encoder->crtc_mask == BIT(PIPE_B))

sys/dev/drm/i915/vlv_dsi.c

1791

intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C);

sys/dev/drm/i915/vlv_dsi.c

1795

intel_encoder->crtc_mask = BIT(PIPE_B);