Symbol: PIPE_A
sys/dev/drm/i915/i915_cmd_parser.c
616
REG32(GEN7_PIPE_DE_LOAD_SL(PIPE_A)),
sys/dev/drm/i915/i915_irq.c
1902
case PIPE_A:
sys/dev/drm/i915/i915_irq.c
2339
intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A);
sys/dev/drm/i915/i915_irq.c
3534
i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
sys/dev/drm/i915/i915_irq.c
4374
i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
sys/dev/drm/i915/i915_irq.c
4552
i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
sys/dev/drm/i915/i915_irq.c
4674
i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
sys/dev/drm/i915/i915_irq.c
4675
i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
sys/dev/drm/i915/i915_irq.c
763
i915_enable_pipestat(dev_priv, PIPE_A,
sys/dev/drm/i915/i915_reg.h
5644
dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \
sys/dev/drm/i915/i915_reg.h
6095
dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \
sys/dev/drm/i915/i915_reg.h
8006
#define LPT_TRANSCONF PCH_TRANSCONF(PIPE_A) /* lpt has only one transcoder */
sys/dev/drm/i915/intel_crt.c
1048
dev_priv->fdi_rx_config = I915_READ(FDI_RX_CTL(PIPE_A)) & fdi_config;
sys/dev/drm/i915/intel_crt.c
226
intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
sys/dev/drm/i915/intel_crt.c
246
intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
sys/dev/drm/i915/intel_crt.c
257
intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
sys/dev/drm/i915/intel_crt.c
292
intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
sys/dev/drm/i915/intel_ddi.c
1127
I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
sys/dev/drm/i915/intel_ddi.c
1135
I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
sys/dev/drm/i915/intel_ddi.c
1136
POSTING_READ(FDI_RX_CTL(PIPE_A));
sys/dev/drm/i915/intel_ddi.c
1141
I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
sys/dev/drm/i915/intel_ddi.c
1171
I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
sys/dev/drm/i915/intel_ddi.c
1175
I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
sys/dev/drm/i915/intel_ddi.c
1176
POSTING_READ(FDI_RX_CTL(PIPE_A));
sys/dev/drm/i915/intel_ddi.c
1182
temp = I915_READ(FDI_RX_MISC(PIPE_A));
sys/dev/drm/i915/intel_ddi.c
1184
I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
sys/dev/drm/i915/intel_ddi.c
1185
POSTING_READ(FDI_RX_MISC(PIPE_A));
sys/dev/drm/i915/intel_ddi.c
1206
I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
sys/dev/drm/i915/intel_ddi.c
1207
POSTING_READ(FDI_RX_CTL(PIPE_A));
sys/dev/drm/i915/intel_ddi.c
1224
temp = I915_READ(FDI_RX_MISC(PIPE_A));
sys/dev/drm/i915/intel_ddi.c
1227
I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
sys/dev/drm/i915/intel_ddi.c
1228
POSTING_READ(FDI_RX_MISC(PIPE_A));
sys/dev/drm/i915/intel_ddi.c
1844
case PIPE_A:
sys/dev/drm/i915/intel_ddi.c
2028
*pipe = PIPE_A;
sys/dev/drm/i915/intel_ddi.c
3117
val = I915_READ(FDI_RX_CTL(PIPE_A));
sys/dev/drm/i915/intel_ddi.c
3119
I915_WRITE(FDI_RX_CTL(PIPE_A), val);
sys/dev/drm/i915/intel_ddi.c
3124
val = I915_READ(FDI_RX_MISC(PIPE_A));
sys/dev/drm/i915/intel_ddi.c
3127
I915_WRITE(FDI_RX_MISC(PIPE_A), val);
sys/dev/drm/i915/intel_ddi.c
3129
val = I915_READ(FDI_RX_CTL(PIPE_A));
sys/dev/drm/i915/intel_ddi.c
3131
I915_WRITE(FDI_RX_CTL(PIPE_A), val);
sys/dev/drm/i915/intel_ddi.c
3133
val = I915_READ(FDI_RX_CTL(PIPE_A));
sys/dev/drm/i915/intel_ddi.c
3135
I915_WRITE(FDI_RX_CTL(PIPE_A), val);
sys/dev/drm/i915/intel_device_info.c
748
info->num_scalers[PIPE_A] = 2;
sys/dev/drm/i915/intel_device_info.c
768
info->num_sprites[PIPE_A] = 2;
sys/dev/drm/i915/intel_device_info.c
814
disabled_mask |= BIT(PIPE_A);
sys/dev/drm/i915/intel_device_info.c
823
case BIT(PIPE_A):
sys/dev/drm/i915/intel_device_info.c
825
case BIT(PIPE_A) | BIT(PIPE_B):
sys/dev/drm/i915/intel_device_info.c
826
case BIT(PIPE_A) | BIT(PIPE_C):
sys/dev/drm/i915/intel_display.c
13771
return pipe == PIPE_A && plane_id == PLANE_PRIMARY;
sys/dev/drm/i915/intel_display.c
14537
crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A);
sys/dev/drm/i915/intel_display.c
1472
if (pipe != PIPE_A) {
sys/dev/drm/i915/intel_display.c
15558
WARN_ON(I915_READ(CURCNTR(PIPE_A)) & MCURSOR_MODE);
sys/dev/drm/i915/intel_display.c
15624
(HAS_PCH_LPT_H(dev_priv) && pch_transcoder == PIPE_A);
sys/dev/drm/i915/intel_display.c
1579
I915_WRITE(DPLL(PIPE_A),
sys/dev/drm/i915/intel_display.c
1580
I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
sys/dev/drm/i915/intel_display.c
15810
enum i915_pipe pipe = PIPE_A;
sys/dev/drm/i915/intel_display.c
1603
if (pipe != PIPE_A)
sys/dev/drm/i915/intel_display.c
1620
if (pipe != PIPE_A)
sys/dev/drm/i915/intel_display.c
1734
assert_fdi_rx_enabled(dev_priv, PIPE_A);
sys/dev/drm/i915/intel_display.c
1737
val = I915_READ(TRANS_CHICKEN2(PIPE_A));
sys/dev/drm/i915/intel_display.c
1739
I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
sys/dev/drm/i915/intel_display.c
1805
val = I915_READ(TRANS_CHICKEN2(PIPE_A));
sys/dev/drm/i915/intel_display.c
1807
I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
sys/dev/drm/i915/intel_display.c
1815
return PIPE_A;
sys/dev/drm/i915/intel_display.c
4668
case PIPE_A:
sys/dev/drm/i915/intel_display.c
4814
assert_pch_transcoder_disabled(dev_priv, PIPE_A);
sys/dev/drm/i915/intel_display.c
4819
ironlake_pch_transcoder_set_timings(crtc, PIPE_A);
sys/dev/drm/i915/intel_display.c
5720
return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
sys/dev/drm/i915/intel_display.c
6536
case PIPE_A:
sys/dev/drm/i915/intel_display.c
6683
(crtc->pipe == PIPE_A || IS_I915G(dev_priv));
sys/dev/drm/i915/intel_display.c
7005
if (crtc->pipe != PIPE_A)
sys/dev/drm/i915/intel_display.c
7022
if (crtc->pipe != PIPE_A)
sys/dev/drm/i915/intel_display.c
7106
if (pipe == PIPE_A)
sys/dev/drm/i915/intel_display.c
7114
if (pipe == PIPE_A)
sys/dev/drm/i915/intel_display.c
8018
if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
sys/dev/drm/i915/intel_display.c
9534
trans_edp_pipe = PIPE_A;
sys/dev/drm/i915/intel_display.c
9644
tmp = I915_READ(FDI_RX_CTL(PIPE_A));
sys/dev/drm/i915/intel_display.c
9962
I915_WRITE_FW(CURCNTR(PIPE_A), 0);
sys/dev/drm/i915/intel_display.c
9963
I915_WRITE_FW(CURBASE(PIPE_A), base);
sys/dev/drm/i915/intel_display.c
9965
I915_WRITE_FW(CURPOS(PIPE_A), pos);
sys/dev/drm/i915/intel_display.c
9966
I915_WRITE_FW(CURCNTR(PIPE_A), cntl);
sys/dev/drm/i915/intel_display.c
9972
I915_WRITE_FW(CURPOS(PIPE_A), pos);
sys/dev/drm/i915/intel_display.c
9975
POSTING_READ_FW(CURCNTR(PIPE_A));
sys/dev/drm/i915/intel_display.c
9993
power_domain = POWER_DOMAIN_PIPE(PIPE_A);
sys/dev/drm/i915/intel_display.c
9997
ret = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
sys/dev/drm/i915/intel_display.c
9999
*pipe = PIPE_A;
sys/dev/drm/i915/intel_dp.c
2851
*pipe = PIPE_A;
sys/dev/drm/i915/intel_dp.c
3252
if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
sys/dev/drm/i915/intel_dp.c
3865
intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
sys/dev/drm/i915/intel_dp.c
3866
intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
sys/dev/drm/i915/intel_dp.c
3870
DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) |
sys/dev/drm/i915/intel_dp.c
3879
intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
sys/dev/drm/i915/intel_dp.c
3880
intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
sys/dev/drm/i915/intel_dp.c
3881
intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
sys/dev/drm/i915/intel_dp.c
6507
if (pipe != PIPE_A && pipe != PIPE_B)
sys/dev/drm/i915/intel_dp.c
6510
if (pipe != PIPE_A && pipe != PIPE_B)
sys/dev/drm/i915/intel_dp.c
6511
pipe = PIPE_A;
sys/dev/drm/i915/intel_dp.c
784
unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
sys/dev/drm/i915/intel_dp.c
838
pipe = PIPE_A;
sys/dev/drm/i915/intel_dp.c
913
for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
sys/dev/drm/i915/intel_drv.h
1240
case PIPE_A:
sys/dev/drm/i915/intel_fifo_underrun.c
130
uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
sys/dev/drm/i915/intel_fifo_underrun.c
196
uint32_t bit = (pch_transcoder == PIPE_A) ?
sys/dev/drm/i915/intel_hdmi.c
1418
intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
sys/dev/drm/i915/intel_hdmi.c
1419
intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
sys/dev/drm/i915/intel_hdmi.c
1422
temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A);
sys/dev/drm/i915/intel_hdmi.c
1436
intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
sys/dev/drm/i915/intel_hdmi.c
1437
intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
sys/dev/drm/i915/intel_hdmi.c
1438
intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
sys/dev/drm/i915/intel_panel.c
1640
if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
sys/dev/drm/i915/intel_panel.c
499
if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
sys/dev/drm/i915/intel_pm.c
1016
FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) |
sys/dev/drm/i915/intel_pm.c
1017
FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) |
sys/dev/drm/i915/intel_pm.c
1018
FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));
sys/dev/drm/i915/intel_pm.c
1028
FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) |
sys/dev/drm/i915/intel_pm.c
1029
FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) |
sys/dev/drm/i915/intel_pm.c
1030
FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));
sys/dev/drm/i915/intel_pm.c
1971
case PIPE_A:
sys/dev/drm/i915/intel_pm.c
3548
if (dirty & WM_DIRTY_PIPE(PIPE_A))
sys/dev/drm/i915/intel_pm.c
3555
if (dirty & WM_DIRTY_LINETIME(PIPE_A))
sys/dev/drm/i915/intel_pm.c
3556
I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
sys/dev/drm/i915/intel_pm.c
482
case PIPE_A:
sys/dev/drm/i915/intel_pm.c
5626
[PIPE_A] = WM0_PIPEA_ILK,
sys/dev/drm/i915/intel_pm.c
5682
wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEA);
sys/dev/drm/i915/intel_pm.c
5689
wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);
sys/dev/drm/i915/intel_pm.c
5690
wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEA);
sys/dev/drm/i915/intel_pm.c
5722
wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEA);
sys/dev/drm/i915/intel_pm.c
5725
wm->pipe[PIPE_A].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEB);
sys/dev/drm/i915/intel_pm.c
5726
wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);
sys/dev/drm/i915/intel_pm.c
5727
wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEA);
sys/dev/drm/i915/intel_pm.c
5753
wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
sys/dev/drm/i915/intel_pm.c
5754
wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
sys/dev/drm/i915/intel_pm.c
5755
wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8;
sys/dev/drm/i915/intel_pm.c
5766
wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
sys/dev/drm/i915/intel_pm.c
5767
wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
sys/dev/drm/i915/intel_pm.c
5768
wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8;
sys/dev/drm/i915/intel_pm.c
8741
I915_WRITE(TRANS_CHICKEN1(PIPE_A),
sys/dev/drm/i915/intel_pm.c
8742
I915_READ(TRANS_CHICKEN1(PIPE_A)) |
sys/dev/drm/i915/intel_pm.c
940
FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));
sys/dev/drm/i915/intel_pm.c
946
FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |
sys/dev/drm/i915/intel_pm.c
947
FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));
sys/dev/drm/i915/intel_pm.c
990
FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));
sys/dev/drm/i915/intel_pm.c
992
FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE1], SPRITEB) |
sys/dev/drm/i915/intel_pm.c
993
FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |
sys/dev/drm/i915/intel_pm.c
994
FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));
sys/dev/drm/i915/intel_runtime_pm.c
1001
if (pipe != PIPE_A)
sys/dev/drm/i915/intel_runtime_pm.c
1224
pipe = PIPE_A;
sys/dev/drm/i915/intel_runtime_pm.c
1287
assert_pll_disabled(dev_priv, PIPE_A);
sys/dev/drm/i915/intel_runtime_pm.c
1311
enum i915_pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C;
sys/dev/drm/i915/intel_runtime_pm.c
1434
enum i915_pipe pipe = PIPE_A;
sys/dev/drm/i915/intel_runtime_pm.c
1464
enum i915_pipe pipe = PIPE_A;
sys/dev/drm/i915/intel_runtime_pm.c
3634
uint32_t status = I915_READ(DPLL(PIPE_A));
sys/dev/drm/i915/intel_runtime_pm.c
844
if ((I915_READ(PIPECONF(PIPE_A)) & PIPECONF_ENABLE) == 0)
sys/dev/drm/i915/intel_runtime_pm.c
845
i830_enable_pipe(dev_priv, PIPE_A);
sys/dev/drm/i915/intel_runtime_pm.c
854
i830_disable_pipe(dev_priv, PIPE_A);
sys/dev/drm/i915/intel_runtime_pm.c
860
return I915_READ(PIPECONF(PIPE_A)) & PIPECONF_ENABLE &&
sys/dev/drm/i915/intel_sdvo.c
1558
intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
sys/dev/drm/i915/intel_sdvo.c
1559
intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
sys/dev/drm/i915/intel_sdvo.c
1562
temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A);
sys/dev/drm/i915/intel_sdvo.c
1568
intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
sys/dev/drm/i915/intel_sdvo.c
1569
intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
sys/dev/drm/i915/intel_sdvo.c
1570
intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
sys/dev/drm/i915/vlv_dsi.c
1077
*pipe = port == PORT_A ? PIPE_A : PIPE_B;
sys/dev/drm/i915/vlv_dsi.c
1791
intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C);
sys/dev/drm/i915/vlv_dsi.c
1793
intel_encoder->crtc_mask = BIT(PIPE_A);