sys/dev/drm/i915/intel_display.c

1274

cur_state = !!(val & PIPECONF_ENABLE);

sys/dev/drm/i915/intel_display.c

15542

I915_WRITE(PIPECONF(pipe), PIPECONF_ENABLE | PIPECONF_PROGRESSIVE);

sys/dev/drm/i915/intel_display.c

1856

if (val & PIPECONF_ENABLE) {

sys/dev/drm/i915/intel_display.c

1862

I915_WRITE(reg, val | PIPECONF_ENABLE);

sys/dev/drm/i915/intel_display.c

1895

if ((val & PIPECONF_ENABLE) == 0)

sys/dev/drm/i915/intel_display.c

1907

val &= ~PIPECONF_ENABLE;

sys/dev/drm/i915/intel_display.c

1910

if ((val & PIPECONF_ENABLE) == 0)

sys/dev/drm/i915/intel_display.c

7560

pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;

sys/dev/drm/i915/intel_display.c

7984

if (!(tmp & PIPECONF_ENABLE))

sys/dev/drm/i915/intel_display.c

9057

if (!(tmp & PIPECONF_ENABLE))

sys/dev/drm/i915/intel_display.c

9555

return tmp & PIPECONF_ENABLE;

sys/dev/drm/i915/intel_runtime_pm.c

844

if ((I915_READ(PIPECONF(PIPE_A)) & PIPECONF_ENABLE) == 0)

sys/dev/drm/i915/intel_runtime_pm.c

846

if ((I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE) == 0)

sys/dev/drm/i915/intel_runtime_pm.c

860

return I915_READ(PIPECONF(PIPE_A)) & PIPECONF_ENABLE &&

sys/dev/drm/i915/intel_runtime_pm.c

861

I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE;

sys/dev/drm/i915/vlv_dsi.c

1053

enabled = I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE;