sys/dev/drm/i915/intel_crt.c

650

pipeconf_reg = PIPECONF(pipe);

sys/dev/drm/i915/intel_display.c

1093

i915_reg_t reg = PIPECONF(cpu_transcoder);

sys/dev/drm/i915/intel_display.c

1273

u32 val = I915_READ(PIPECONF(cpu_transcoder));

sys/dev/drm/i915/intel_display.c

15542

I915_WRITE(PIPECONF(pipe), PIPECONF_ENABLE | PIPECONF_PROGRESSIVE);

sys/dev/drm/i915/intel_display.c

15543

POSTING_READ(PIPECONF(pipe));

sys/dev/drm/i915/intel_display.c

15561

I915_WRITE(PIPECONF(pipe), 0);

sys/dev/drm/i915/intel_display.c

15562

POSTING_READ(PIPECONF(pipe));

sys/dev/drm/i915/intel_display.c

15636

i915_reg_t reg = PIPECONF(cpu_transcoder);

sys/dev/drm/i915/intel_display.c

16374

error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));

sys/dev/drm/i915/intel_display.c

1695

pipeconf_val = I915_READ(PIPECONF(pipe));

sys/dev/drm/i915/intel_display.c

1742

pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));

sys/dev/drm/i915/intel_display.c

1854

reg = PIPECONF(cpu_transcoder);

sys/dev/drm/i915/intel_display.c

1893

reg = PIPECONF(cpu_transcoder);

sys/dev/drm/i915/intel_display.c

4356

temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;

sys/dev/drm/i915/intel_display.c

4428

temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;

sys/dev/drm/i915/intel_display.c

4456

temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;

sys/dev/drm/i915/intel_display.c

4781

u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;

sys/dev/drm/i915/intel_display.c

7506

if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {

sys/dev/drm/i915/intel_display.c

7560

pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;

sys/dev/drm/i915/intel_display.c

7602

I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);

sys/dev/drm/i915/intel_display.c

7603

POSTING_READ(PIPECONF(intel_crtc->pipe));

sys/dev/drm/i915/intel_display.c

7983

tmp = I915_READ(PIPECONF(crtc->pipe));

sys/dev/drm/i915/intel_display.c

8547

I915_WRITE(PIPECONF(pipe), val);

sys/dev/drm/i915/intel_display.c

8548

POSTING_READ(PIPECONF(pipe));

sys/dev/drm/i915/intel_display.c

8566

I915_WRITE(PIPECONF(cpu_transcoder), val);

sys/dev/drm/i915/intel_display.c

8567

POSTING_READ(PIPECONF(cpu_transcoder));

sys/dev/drm/i915/intel_display.c

9056

tmp = I915_READ(PIPECONF(crtc->pipe));

sys/dev/drm/i915/intel_display.c

9553

tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));

sys/dev/drm/i915/intel_dp.c

6116

i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);

sys/dev/drm/i915/intel_runtime_pm.c

844

if ((I915_READ(PIPECONF(PIPE_A)) & PIPECONF_ENABLE) == 0)

sys/dev/drm/i915/intel_runtime_pm.c

846

if ((I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE) == 0)

sys/dev/drm/i915/intel_runtime_pm.c

860

return I915_READ(PIPECONF(PIPE_A)) & PIPECONF_ENABLE &&

sys/dev/drm/i915/intel_runtime_pm.c

861

I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE;

sys/dev/drm/i915/vlv_dsi.c

1053

enabled = I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE;