sys/dev/drm/i915/intel_display.c

8119

u32 temp = I915_READ(PCH_DPLL(i));

sys/dev/drm/i915/intel_dpll_mgr.c

352

val = I915_READ(PCH_DPLL(id));

sys/dev/drm/i915/intel_dpll_mgr.c

392

I915_WRITE(PCH_DPLL(id), pll->state.hw_state.dpll);

sys/dev/drm/i915/intel_dpll_mgr.c

395

POSTING_READ(PCH_DPLL(id));

sys/dev/drm/i915/intel_dpll_mgr.c

403

I915_WRITE(PCH_DPLL(id), pll->state.hw_state.dpll);

sys/dev/drm/i915/intel_dpll_mgr.c

404

POSTING_READ(PCH_DPLL(id));

sys/dev/drm/i915/intel_dpll_mgr.c

421

I915_WRITE(PCH_DPLL(id), 0);

sys/dev/drm/i915/intel_dpll_mgr.c

422

POSTING_READ(PCH_DPLL(id));