ATA_INL
ATA_INL(ch->r_io[idx].res, ch->r_io[idx].offset)
MAX(flsl(ATA_INL(ctlr->r_res2, ATA_AHCI_PI)),
(ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_NPMASK) + 1);
version = ATA_INL(ctlr->r_res2, ATA_AHCI_VS);
(ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_NPMASK) + 1);
if ((ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) & ATA_AHCI_GHC_HR) == 0)
ATA_OUTL(ctlr->r_res2, ATA_AHCI_IS, ATA_INL(ctlr->r_res2, ATA_AHCI_IS));
ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) | ATA_AHCI_GHC_IE);
u_int32_t action = ATA_INL(ctlr->r_res2, ATA_AHCI_IS);
u_int32_t istatus = ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset);
u_int32_t cstatus = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CI + offset);
u_int32_t cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
} while (ATA_INL(ctlr->r_res2,
ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) |
ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) &
tf_data = ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + (ch->unit<<7));
tf_data = ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + offset);
cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
while (ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) & ATA_AHCI_P_CMD_CR);
if (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_CLO) {
cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
while (ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD+offset)&ATA_AHCI_P_CMD_CLO);
ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset));
cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
while ((val = ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + offset)) &
return ATA_INL(ctlr->r_res2, ATA_AHCI_P_SIG + offset);
if (!(ATA_INL(ctlr->r_res2, ATA_AHCI_PI) & (1 << ch->unit))) {
cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
if (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_64BIT)
ATA_INL(ctlr->r_res2, 0x04) | (0x01 << (ch->unit << 3)));
u_int32_t cause = ATA_INL(ctlr->r_res1, 0x01d60);
if (ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)
req_in = ATA_INL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch));
if (!(ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)) {
while (!(ATA_INL(ctlr->r_res1,
u_int32_t icr = ATA_INL(ctlr->r_res1, offset);
rsp_in = ATA_INL(ctlr->r_res1, 0x02020 + ATA_MV_EDMA_BASE(ch));
rsp_out = ATA_INL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch));
while ((ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001))
if (ATA_INL(ctlr->r_res1, 0x00d00) & 0x00000004)
ATA_INL(ctlr->r_res2, 0x0400) & 0xfffffff9);
istatus = ATA_INL(ctlr->r_res2, offset);
u_int32_t dimm = ATA_INL(ctlr->r_res2, 0x000c0080);
ATA_INL(ctlr->r_res2, 0x000c0088) & (1<<16) ?
(ATA_INL(ctlr->r_res2, 0x000c000c) & 0xffff0000));
ctlr->channels = ((ATA_INL(ctlr->r_res2, 0x48) & 0x01) > 0) +
((ATA_INL(ctlr->r_res2, 0x48) & 0x02) > 0) + 2;
ATA_OUTL(ctlr->r_res2, 0x44, ATA_INL(ctlr->r_res2, 0x44) | 0x2000);
if (ATA_INL(ctlr->r_res1, 0x1c) & (ch->unit ? 0x00004000 : 0x00000400)) {
(ATA_INL(ctlr->r_res2,
vector = ATA_INL(ctlr->r_res2, 0x040);
vector = ATA_INL(ctlr->r_res2, fake_reg);
status = ATA_INL(ctlr->r_res2, stat_reg);
(ATA_INL(ctlr->r_res2, 0xc0260 + (ch->unit << 7)) &
(ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f) | (1 << 11));
(ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f));
(ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) &
(ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) &
(ATA_INL(ctlr->r_res2, 0x414 + (ch->unit << 8)) &
u_int32_t vector = ATA_INL(ctlr->r_res2, 0x000c0480);
(ATA_INL(ctlr->r_res2, 0x10 + offset0) & 0x00000010))
if (ATA_INL(ctlr->r_res2, 0xa0 + offset1) & 0x00000800)
u_int32_t action = ATA_INL(ctlr->r_res1, 0x0044);
u_int32_t istatus = ATA_INL(ctlr->r_res2, 0x1008 + offset);
if ((error = ATA_INL(ctlr->r_res2, 0x1024 + offset))) {
if (ATA_INL(ctlr->r_res2, 0x1008 + offset) & 0x00040000)
if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00010000)
if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00040000)