sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

800

PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9), 0, 0, 0));

sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

839

ib->ptr[0] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9), 0, 0, PACKETJ_TYPE0);

sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

842

ib->ptr[i] = PACKETJ(0, 0, 0, PACKETJ_TYPE6);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1623

PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1626

amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1642

PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1645

amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1665

PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_DATA0), 0, 0, PACKETJ_TYPE0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1669

PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_DATA1), 0, 0, PACKETJ_TYPE0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1673

PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1677

PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1681

PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_CMD), 0, 0, PACKETJ_TYPE0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1685

PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_CMD), 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE4));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1689

PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1693

PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1697

PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1701

PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1705

PACKETJ(0, 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE2));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1709

PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1713

PACKETJ(0, 0, 0, PACKETJ_TYPE0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1717

amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE7));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1736

PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_IB_VMID), 0, 0, PACKETJ_TYPE0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1740

PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JPEG_VMID), 0, 0, PACKETJ_TYPE0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1744

PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1748

PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1752

PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_IB_SIZE), 0, 0, PACKETJ_TYPE0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1756

PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1760

PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1764

PACKETJ(0, 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE2));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1768

PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1772

PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1776

PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_STATUS), 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE3));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1788

PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1792

PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1796

PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1801

PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1805

PACKETJ(0, 0, 0, PACKETJ_TYPE3));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1832

PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1837

PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1841

PACKETJ(0, 0, 0, PACKETJ_TYPE0));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1853

amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1861

ring->ring[(*ptr)++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1865

ring->ring[(*ptr)++] = PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1868

ring->ring[(*ptr)++] = PACKETJ(0, 0, 0, PACKETJ_TYPE0);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1893

ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE2);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1915

ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1917

ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1919

ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1923

ring->ring[ptr++] = PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1926

ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE3);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1932

ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE6);