sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2527

amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2535

amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4070

buffer[count++] = cpu_to_le32(ext->reg_index - PACKET3_SET_CONTEXT_REG_START);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4080

buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1279

PACKET3_SET_CONTEXT_REG_START);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1290

PACKET3_SET_CONTEXT_REG_START);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4270

ext->reg_index - PACKET3_SET_CONTEXT_REG_START);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4278

amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2638

ext->reg_index - PACKET3_SET_CONTEXT_REG_START);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

905

PACKET3_SET_CONTEXT_REG_START);

sys/dev/drm/radeon/cik.c

6759

buffer[count++] = cpu_to_le32(PA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);

sys/dev/drm/radeon/evergreen_cs.c

2316

start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_START;

sys/dev/drm/radeon/evergreen_cs.c

2318

if ((start_reg < PACKET3_SET_CONTEXT_REG_START) ||

sys/dev/drm/radeon/evergreen_cs.c

2627

allowed_reg_base -= PACKET3_SET_CONTEXT_REG_START;

sys/dev/drm/radeon/evergreen_cs.c

3502

allowed_reg_base -= PACKET3_SET_CONTEXT_REG_START;

sys/dev/drm/radeon/si.c

5734

buffer[count++] = cpu_to_le32(PA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);