PACKET3_SET_CONFIG_REG_START
PACKET3_SET_CONFIG_REG_START) >> 2));
start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START;
if ((start_reg < PACKET3_SET_CONFIG_REG_START) ||
start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START;
if ((start_reg < PACKET3_SET_CONFIG_REG_START) ||
PACKET3_SET_CONFIG_REG_START) >> 2));
radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
PACKET3_SET_CONFIG_REG_START) >> 2));
radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START;
if ((start_reg < PACKET3_SET_CONFIG_REG_START) ||