sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

851

amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));

sys/dev/drm/amd/amdgpu/cikd.h

229

#define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2078

amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2128

amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2141

amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2145

amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2167

amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2179

amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2208

amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2243

amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2248

header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2250

header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2270

amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2295

amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2330

ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2509

amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2515

amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2518

amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2526

PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2534

amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2539

amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2542

amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2545

amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3189

amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3201

amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3203

amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3230

amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3243

amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3247

amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3249

amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3259

amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4058

buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4061

buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4069

cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4079

buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2));

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4105

buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4108

buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4175

amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4183

amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4191

amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4199

amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

5050

.nop = PACKET3(PACKET3_NOP, 0x3FFF),

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

5082

.nop = PACKET3(PACKET3_NOP, 0x3FFF),

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1266

buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1269

buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1277

cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1288

buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1294

buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1297

buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1671

ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1677

ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1683

ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1691

ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1697

ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1703

ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1709

ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1717

ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1723

ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1729

ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1735

ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1743

ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4256

amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4259

amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4267

PACKET3(PACKET3_SET_CONTEXT_REG,

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4277

amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4282

amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4285

amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4289

amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4447

amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4461

amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4893

amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

5234

amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

5242

amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

5250

amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

5258

amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6113

amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6126

amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6130

amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6142

header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6144

header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6171

amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6188

amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6208

amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6227

amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6240

amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6365

amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6385

amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6394

amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6405

amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6437

amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6446

amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6473

amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6502

amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6893

.nop = PACKET3(PACKET3_NOP, 0x3FFF),

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6938

.nop = PACKET3(PACKET3_NOP, 0x3FFF),

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6968

.nop = PACKET3(PACKET3_NOP, 0x3FFF),

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

7199

amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt_ce));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

7232

amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt_de));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

854

amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

902

ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1648

amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2624

amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2627

amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2635

PACKET3(PACKET3_SET_CONTEXT_REG,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2645

amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2648

amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2651

amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2656

amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG,1));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2838

amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2852

amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3385

amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

359

amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

373

amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4083

header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4085

header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

411

amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4113

amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4132

amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4177

amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4320

amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4329

amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4340

amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4353

amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4375

amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4387

amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4420

amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4428

amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4454

amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4482

amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

459

ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4739

.nop = PACKET3(PACKET3_NOP, 0x3FFF),

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4790

.nop = PACKET3(PACKET3_NOP, 0x3FFF),

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4825

.nop = PACKET3(PACKET3_NOP, 0x3FFF),

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

892

buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

895

buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

903

cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

914

buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

917

buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));

sys/dev/drm/amd/amdgpu/soc15d.h

54

#define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)

sys/dev/drm/amd/amdgpu/vid.h

111

#define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)

sys/dev/drm/radeon/cik.c

3490

radeon_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));

sys/dev/drm/radeon/cik.c

3546

radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));

sys/dev/drm/radeon/cik.c

3575

radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));

sys/dev/drm/radeon/cik.c

3587

radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));

sys/dev/drm/radeon/cik.c

3614

radeon_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));

sys/dev/drm/radeon/cik.c

3645

radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1));

sys/dev/drm/radeon/cik.c

3651

radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));

sys/dev/drm/radeon/cik.c

3706

radeon_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));

sys/dev/drm/radeon/cik.c

3753

radeon_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));

sys/dev/drm/radeon/cik.c

3756

header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);

sys/dev/drm/radeon/cik.c

3761

radeon_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));

sys/dev/drm/radeon/cik.c

3767

radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));

sys/dev/drm/radeon/cik.c

3774

header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);

sys/dev/drm/radeon/cik.c

3815

ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);

sys/dev/drm/radeon/cik.c

4016

radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));

sys/dev/drm/radeon/cik.c

4022

radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));

sys/dev/drm/radeon/cik.c

4025

radeon_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));

sys/dev/drm/radeon/cik.c

4032

radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));

sys/dev/drm/radeon/cik.c

4036

radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));

sys/dev/drm/radeon/cik.c

4039

radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));

sys/dev/drm/radeon/cik.c

5709

radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));

sys/dev/drm/radeon/cik.c

5723

radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));

sys/dev/drm/radeon/cik.c

5730

radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 6));

sys/dev/drm/radeon/cik.c

5741

radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));

sys/dev/drm/radeon/cik.c

5752

radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));

sys/dev/drm/radeon/cik.c

5760

radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));

sys/dev/drm/radeon/cik.c

5773

radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));

sys/dev/drm/radeon/cik.c

6737

buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));

sys/dev/drm/radeon/cik.c

6740

buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));

sys/dev/drm/radeon/cik.c

6748

cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));

sys/dev/drm/radeon/cik.c

6758

buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2));

sys/dev/drm/radeon/cik.c

6784

buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));

sys/dev/drm/radeon/cik.c

6787

buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));

sys/dev/drm/radeon/cik.c

8421

nop = PACKET3(PACKET3_NOP, 0x3FFF);

sys/dev/drm/radeon/cik.c

8425

nop = PACKET3(PACKET3_NOP, 0x3FFF);

sys/dev/drm/radeon/cikd.h

1695

#define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)

sys/dev/drm/radeon/evergreen.c

2918

radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));

sys/dev/drm/radeon/evergreen.c

2923

radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));

sys/dev/drm/radeon/evergreen.c

2929

radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3));

sys/dev/drm/radeon/evergreen.c

2936

radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));

sys/dev/drm/radeon/evergreen.c

2990

radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));

sys/dev/drm/radeon/evergreen.c

3009

radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));

sys/dev/drm/radeon/evergreen.c

3015

radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));

sys/dev/drm/radeon/evergreen.c

3019

radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));

sys/dev/drm/radeon/ni.c

1421

radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));

sys/dev/drm/radeon/ni.c

1427

radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));

sys/dev/drm/radeon/ni.c

1443

radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));

sys/dev/drm/radeon/ni.c

1448

radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));

sys/dev/drm/radeon/ni.c

1454

radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));

sys/dev/drm/radeon/ni.c

1464

radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));

sys/dev/drm/radeon/ni.c

1570

radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));

sys/dev/drm/radeon/ni.c

1588

radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));

sys/dev/drm/radeon/ni.c

1594

radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));

sys/dev/drm/radeon/ni.c

1598

radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));

sys/dev/drm/radeon/ni.c

2719

radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));

sys/dev/drm/radeon/ni.c

2729

radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));

sys/dev/drm/radeon/r100.c

923

radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8));

sys/dev/drm/radeon/r600.c

2706

radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));

sys/dev/drm/radeon/r600.c

2851

radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));

sys/dev/drm/radeon/r600.c

2889

radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));

sys/dev/drm/radeon/r600.c

2895

radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));

sys/dev/drm/radeon/r600.c

2903

radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));

sys/dev/drm/radeon/r600.c

2908

radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));

sys/dev/drm/radeon/r600.c

2911

radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));

sys/dev/drm/radeon/r600.c

2915

radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));

sys/dev/drm/radeon/r600.c

2946

radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1));

sys/dev/drm/radeon/r600.c

2953

radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));

sys/dev/drm/radeon/r600.c

3000

radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));

sys/dev/drm/radeon/r600.c

3011

radeon_ring_write(ring, PACKET3(PACKET3_CP_DMA, 4));

sys/dev/drm/radeon/r600.c

3020

radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));

sys/dev/drm/radeon/r600.c

3387

radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));

sys/dev/drm/radeon/r600.c

3393

radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3));

sys/dev/drm/radeon/r600.c

3400

radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));

sys/dev/drm/radeon/r600.c

3429

ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);

sys/dev/drm/radeon/si.c

3367

radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));

sys/dev/drm/radeon/si.c

3370

radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));

sys/dev/drm/radeon/si.c

3379

radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));

sys/dev/drm/radeon/si.c

3398

radeon_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));

sys/dev/drm/radeon/si.c

3401

header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);

sys/dev/drm/radeon/si.c

3406

radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));

sys/dev/drm/radeon/si.c

3412

radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));

sys/dev/drm/radeon/si.c

3419

header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);

sys/dev/drm/radeon/si.c

3433

radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));

sys/dev/drm/radeon/si.c

3436

radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));

sys/dev/drm/radeon/si.c

3558

radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));

sys/dev/drm/radeon/si.c

3567

radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));

sys/dev/drm/radeon/si.c

3582

radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));

sys/dev/drm/radeon/si.c

3588

radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));

sys/dev/drm/radeon/si.c

3592

radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));

sys/dev/drm/radeon/si.c

3595

radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));

sys/dev/drm/radeon/si.c

5066

radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));

sys/dev/drm/radeon/si.c

5081

radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));

sys/dev/drm/radeon/si.c

5089

radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));

sys/dev/drm/radeon/si.c

5097

radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));

sys/dev/drm/radeon/si.c

5107

radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));

sys/dev/drm/radeon/si.c

5712

buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));

sys/dev/drm/radeon/si.c

5715

buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));

sys/dev/drm/radeon/si.c

5723

cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));

sys/dev/drm/radeon/si.c

5733

buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));

sys/dev/drm/radeon/si.c

5754

buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));

sys/dev/drm/radeon/si.c

5757

buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));

sys/dev/drm/radeon/sid.h

1599

#define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)